Search

Belur V. Keshavan

Examiner (ID: 12700)

Most Active Art Unit
2825
Art Unit(s)
2825, 2823
Total Applications
284
Issued Applications
267
Pending Applications
6
Abandoned Applications
11

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18998928 [patent_doc_number] => 11915782 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Semiconductor device and electronic device including the same [patent_app_type] => utility [patent_app_number] => 17/407585 [patent_app_country] => US [patent_app_date] => 2021-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9238 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17407585 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/407585
Semiconductor device and electronic device including the same Aug 19, 2021 Issued
Array ( [id] => 18766752 [patent_doc_number] => 11817159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Circuit for detecting anti-fuse memory cell state and memory [patent_app_type] => utility [patent_app_number] => 17/445372 [patent_app_country] => US [patent_app_date] => 2021-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4601 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17445372 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/445372
Circuit for detecting anti-fuse memory cell state and memory Aug 17, 2021 Issued
Array ( [id] => 17978407 [patent_doc_number] => 11495279 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-08 [patent_title] => Managing write disturb for units of memory in a memory sub-system using a randomized refresh period [patent_app_type] => utility [patent_app_number] => 17/402984 [patent_app_country] => US [patent_app_date] => 2021-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8208 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17402984 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/402984
Managing write disturb for units of memory in a memory sub-system using a randomized refresh period Aug 15, 2021 Issued
Array ( [id] => 18578741 [patent_doc_number] => 11735280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Memory device and operating method of the same [patent_app_type] => utility [patent_app_number] => 17/401907 [patent_app_country] => US [patent_app_date] => 2021-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11813 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17401907 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/401907
Memory device and operating method of the same Aug 12, 2021 Issued
Array ( [id] => 18782003 [patent_doc_number] => 11823768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Drive circuit and memory chip [patent_app_type] => utility [patent_app_number] => 17/401270 [patent_app_country] => US [patent_app_date] => 2021-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6600 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17401270 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/401270
Drive circuit and memory chip Aug 11, 2021 Issued
Array ( [id] => 18918993 [patent_doc_number] => 11881281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-23 [patent_title] => Dual reference voltage generator, equalizer circuit, and memory [patent_app_type] => utility [patent_app_number] => 17/398180 [patent_app_country] => US [patent_app_date] => 2021-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6265 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17398180 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/398180
Dual reference voltage generator, equalizer circuit, and memory Aug 9, 2021 Issued
Array ( [id] => 20507910 [patent_doc_number] => 12542192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Stacked memory and manufacturing method therefor [patent_app_type] => utility [patent_app_number] => 18/681760 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3689 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18681760 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/681760
Stacked memory and manufacturing method therefor Aug 5, 2021 Issued
Array ( [id] => 17878381 [patent_doc_number] => 11450402 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-20 [patent_title] => Sensing circuit and test device [patent_app_type] => utility [patent_app_number] => 17/392273 [patent_app_country] => US [patent_app_date] => 2021-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7950 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17392273 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/392273
Sensing circuit and test device Aug 2, 2021 Issued
Array ( [id] => 18669701 [patent_doc_number] => 11776611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Managing write disturb for units of a memory device using weighted write disturb counts [patent_app_type] => utility [patent_app_number] => 17/393013 [patent_app_country] => US [patent_app_date] => 2021-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 9415 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17393013 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/393013
Managing write disturb for units of a memory device using weighted write disturb counts Aug 2, 2021 Issued
Array ( [id] => 18219334 [patent_doc_number] => 11594280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Content addressable memory device having electrically floating body transistor [patent_app_type] => utility [patent_app_number] => 17/390998 [patent_app_country] => US [patent_app_date] => 2021-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 103 [patent_figures_cnt] => 139 [patent_no_of_words] => 29436 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17390998 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/390998
Content addressable memory device having electrically floating body transistor Jul 31, 2021 Issued
Array ( [id] => 18890831 [patent_doc_number] => 11869608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Anti-fuse unit and anti-fuse array [patent_app_type] => utility [patent_app_number] => 17/384945 [patent_app_country] => US [patent_app_date] => 2021-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2657 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17384945 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/384945
Anti-fuse unit and anti-fuse array Jul 25, 2021 Issued
Array ( [id] => 18159610 [patent_doc_number] => 20230026202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => FUSE DELAY OF A COMMAND IN A MEMORY PACKAGE [patent_app_type] => utility [patent_app_number] => 17/381057 [patent_app_country] => US [patent_app_date] => 2021-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6301 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17381057 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/381057
Fuse delay of a command in a memory package Jul 19, 2021 Issued
Array ( [id] => 17359605 [patent_doc_number] => 20220020401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => MEMORY DEVICE AND METHOD FOR INPUT AND OUTPUT BUFFER CONTROL THEREOF [patent_app_type] => utility [patent_app_number] => 17/373787 [patent_app_country] => US [patent_app_date] => 2021-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17373787 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/373787
Memory device and method for input and output buffer control thereof Jul 12, 2021 Issued
Array ( [id] => 17847702 [patent_doc_number] => 11437086 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Phase clock correction [patent_app_type] => utility [patent_app_number] => 17/374349 [patent_app_country] => US [patent_app_date] => 2021-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 16372 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17374349 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/374349
Phase clock correction Jul 12, 2021 Issued
Array ( [id] => 17203224 [patent_doc_number] => 20210343319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => FIRST ORDER MEMORY-LESS DYNAMIC ELEMENT MATCHING TECHNIQUE [patent_app_type] => utility [patent_app_number] => 17/374304 [patent_app_country] => US [patent_app_date] => 2021-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11435 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17374304 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/374304
First order memory-less dynamic element matching technique Jul 12, 2021 Issued
Array ( [id] => 17691838 [patent_doc_number] => 20220199131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => APPARATUS, MEMORY CONTROLLER, MEMORY DEVICE, MEMORY SYSTEM, AND METHOD FOR CLOCK SWITCHING AND LOW POWER CONSUMPTION [patent_app_type] => utility [patent_app_number] => 17/372672 [patent_app_country] => US [patent_app_date] => 2021-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18259 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17372672 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/372672
Apparatus, memory controller, memory device, memory system, and method for clock switching and low power consumption Jul 11, 2021 Issued
Array ( [id] => 17978405 [patent_doc_number] => 11495277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Apparatus performing read operation [patent_app_type] => utility [patent_app_number] => 17/365636 [patent_app_country] => US [patent_app_date] => 2021-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10176 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17365636 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/365636
Apparatus performing read operation Jun 30, 2021 Issued
Array ( [id] => 18080730 [patent_doc_number] => 20220406342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => Sense Amplifier Mapping and Control Scheme for Non-Volatile Memory [patent_app_type] => utility [patent_app_number] => 17/354613 [patent_app_country] => US [patent_app_date] => 2021-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17358 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17354613 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/354613
Sense amplifier mapping and control scheme for non-volatile memory Jun 21, 2021 Issued
Array ( [id] => 18190424 [patent_doc_number] => 11581025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => High resolution ZQ calibration method using hidden least significant bit (HLSB) [patent_app_type] => utility [patent_app_number] => 17/346853 [patent_app_country] => US [patent_app_date] => 2021-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12281 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17346853 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/346853
High resolution ZQ calibration method using hidden least significant bit (HLSB) Jun 13, 2021 Issued
Array ( [id] => 17862624 [patent_doc_number] => 11443785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Memory device for generating data strobe signal based on pulse amplitude modulation, memory controller, and memory system including the same [patent_app_type] => utility [patent_app_number] => 17/344610 [patent_app_country] => US [patent_app_date] => 2021-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 8894 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17344610 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/344610
Memory device for generating data strobe signal based on pulse amplitude modulation, memory controller, and memory system including the same Jun 9, 2021 Issued
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