
Belur V. Keshavan
Examiner (ID: 18924)
| Most Active Art Unit | 2825 |
| Art Unit(s) | 2823, 2825 |
| Total Applications | 284 |
| Issued Applications | 267 |
| Pending Applications | 6 |
| Abandoned Applications | 11 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 944351
[patent_doc_number] => 06967405
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-11-22
[patent_title] => 'Film for copper diffusion barrier'
[patent_app_type] => utility
[patent_app_number] => 10/670660
[patent_app_country] => US
[patent_app_date] => 2003-09-24
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/967/06967405.pdf
[firstpage_image] =>[orig_patent_app_number] => 10670660
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/670660 | Film for copper diffusion barrier | Sep 23, 2003 | Issued |
Array
(
[id] => 1095909
[patent_doc_number] => 06821833
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-11-23
[patent_title] => 'Method for separately optimizing thin gate dielectric of PMOS and NMOS transistors within the same semiconductor chip and device manufactured thereby'
[patent_app_type] => B1
[patent_app_number] => 10/605110
[patent_app_country] => US
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[pdf_file] => patents/06/821/06821833.pdf
[firstpage_image] =>[orig_patent_app_number] => 10605110
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/605110 | Method for separately optimizing thin gate dielectric of PMOS and NMOS transistors within the same semiconductor chip and device manufactured thereby | Sep 8, 2003 | Issued |
Array
(
[id] => 7264077
[patent_doc_number] => 20040241954
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-02
[patent_title] => 'Method for forming a crown capacitor'
[patent_app_type] => new
[patent_app_number] => 10/653730
[patent_app_country] => US
[patent_app_date] => 2003-09-02
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[pdf_file] => publications/A1/0241/20040241954.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/653730 | Method for forming a crown capacitor | Sep 1, 2003 | Abandoned |
Array
(
[id] => 7383072
[patent_doc_number] => 20040082095
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-29
[patent_title] => 'Method of fabricating a solid-state imaging device'
[patent_app_type] => new
[patent_app_number] => 10/647390
[patent_app_country] => US
[patent_app_date] => 2003-08-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0082/20040082095.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/647390 | Method of fabricating a solid-state imaging device | Aug 25, 2003 | Issued |
Array
(
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[patent_doc_number] => 06797611
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[patent_issue_date] => 2004-09-28
[patent_title] => 'Method of fabricating contact holes on a semiconductor chip'
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[patent_app_date] => 2003-08-03
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/604600 | Method of fabricating contact holes on a semiconductor chip | Aug 2, 2003 | Issued |
Array
(
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[patent_doc_number] => 20040063299
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[patent_issue_date] => 2004-04-01
[patent_title] => 'Semiconductor device and method for fabricating the same'
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Array
(
[id] => 988145
[patent_doc_number] => 06921700
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[patent_title] => 'Method of forming a transistor having multiple channels'
[patent_app_type] => utility
[patent_app_number] => 10/631093
[patent_app_country] => US
[patent_app_date] => 2003-07-31
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/921/06921700.pdf
[firstpage_image] =>[orig_patent_app_number] => 10631093
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/631093 | Method of forming a transistor having multiple channels | Jul 30, 2003 | Issued |
Array
(
[id] => 975419
[patent_doc_number] => 06933181
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-23
[patent_title] => 'Method for fabricating semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/620430
[patent_app_country] => US
[patent_app_date] => 2003-07-17
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/933/06933181.pdf
[firstpage_image] =>[orig_patent_app_number] => 10620430
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/620430 | Method for fabricating semiconductor device | Jul 16, 2003 | Issued |
Array
(
[id] => 7400471
[patent_doc_number] => 20040023444
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[patent_issue_date] => 2004-02-05
[patent_title] => 'Method of manufacturing a semiconductor device'
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[pdf_file] => publications/A1/0023/20040023444.pdf
[firstpage_image] =>[orig_patent_app_number] => 10614110
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/614110 | Method of manufacturing a semiconductor device | Jul 7, 2003 | Issued |
Array
(
[id] => 7433730
[patent_doc_number] => 20040002220
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-01
[patent_title] => 'Method of purging semiconductor manufacturing apparatus and method of manufacturing semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/608020
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[patent_app_date] => 2003-06-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/608020 | Method of purging semiconductor manufacturing apparatus and method of manufacturing semiconductor device | Jun 29, 2003 | Issued |
Array
(
[id] => 7221854
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[patent_title] => 'Coplanar integration of lattice-mismatched semiconductor with silicon via wafer bonding virtual substrates'
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[patent_app_number] => 10/603850
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/603850 | Coplanar integration of lattice-mismatched semiconductor with silicon via wafer bonding virtual substrates | Jun 24, 2003 | Issued |
Array
(
[id] => 1153343
[patent_doc_number] => 06770971
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[patent_issue_date] => 2004-08-03
[patent_title] => 'Semiconductor device and method of fabricating the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/458920 | Semiconductor device and method of fabricating the same | Jun 9, 2003 | Issued |
Array
(
[id] => 7361659
[patent_doc_number] => 20040005118
[patent_country] => US
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[patent_issue_date] => 2004-01-08
[patent_title] => 'Method of manufacturing tapered optical waveguide'
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Array
(
[id] => 1073631
[patent_doc_number] => 06838296
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[patent_issue_date] => 2005-01-04
[patent_title] => 'Device and method for detecting alignment of deep trench capacitors and active areas in DRAM devices'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/448920 | Device and method for detecting alignment of deep trench capacitors and active areas in DRAM devices | May 28, 2003 | Issued |
| 10/432041 | Alignment method in chip mounting device | May 18, 2003 | Abandoned |
Array
(
[id] => 1192920
[patent_doc_number] => 06730548
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[patent_title] => 'Method of fabricating a thin film transistor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/439720 | Method of fabricating a thin film transistor | May 15, 2003 | Issued |
Array
(
[id] => 1002342
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[patent_title] => 'Method of manufacturing an electro-optical device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/420540 | Method of manufacturing an electro-optical device | Apr 20, 2003 | Issued |
Array
(
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[patent_title] => 'High crack resistance nitride process'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/417320 | High crack resistance nitride process | Apr 15, 2003 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/408069 | Tailored insulator properties for devices | Apr 3, 2003 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/401400 | Method for improving planarity of shallow trench isolation using multiple simultaneous tiling systems | Mar 30, 2003 | Issued |