Search

Belur V. Keshavan

Examiner (ID: 18924)

Most Active Art Unit
2825
Art Unit(s)
2823, 2825
Total Applications
284
Issued Applications
267
Pending Applications
6
Abandoned Applications
11

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 944351 [patent_doc_number] => 06967405 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-22 [patent_title] => 'Film for copper diffusion barrier' [patent_app_type] => utility [patent_app_number] => 10/670660 [patent_app_country] => US [patent_app_date] => 2003-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3225 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967405.pdf [firstpage_image] =>[orig_patent_app_number] => 10670660 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/670660
Film for copper diffusion barrier Sep 23, 2003 Issued
Array ( [id] => 1095909 [patent_doc_number] => 06821833 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-23 [patent_title] => 'Method for separately optimizing thin gate dielectric of PMOS and NMOS transistors within the same semiconductor chip and device manufactured thereby' [patent_app_type] => B1 [patent_app_number] => 10/605110 [patent_app_country] => US [patent_app_date] => 2003-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 29 [patent_no_of_words] => 6971 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/821/06821833.pdf [firstpage_image] =>[orig_patent_app_number] => 10605110 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/605110
Method for separately optimizing thin gate dielectric of PMOS and NMOS transistors within the same semiconductor chip and device manufactured thereby Sep 8, 2003 Issued
Array ( [id] => 7264077 [patent_doc_number] => 20040241954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Method for forming a crown capacitor' [patent_app_type] => new [patent_app_number] => 10/653730 [patent_app_country] => US [patent_app_date] => 2003-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1698 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20040241954.pdf [firstpage_image] =>[orig_patent_app_number] => 10653730 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/653730
Method for forming a crown capacitor Sep 1, 2003 Abandoned
Array ( [id] => 7383072 [patent_doc_number] => 20040082095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Method of fabricating a solid-state imaging device' [patent_app_type] => new [patent_app_number] => 10/647390 [patent_app_country] => US [patent_app_date] => 2003-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3028 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20040082095.pdf [firstpage_image] =>[orig_patent_app_number] => 10647390 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/647390
Method of fabricating a solid-state imaging device Aug 25, 2003 Issued
Array ( [id] => 1119824 [patent_doc_number] => 06797611 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-28 [patent_title] => 'Method of fabricating contact holes on a semiconductor chip' [patent_app_type] => B1 [patent_app_number] => 10/604600 [patent_app_country] => US [patent_app_date] => 2003-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2377 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/797/06797611.pdf [firstpage_image] =>[orig_patent_app_number] => 10604600 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/604600
Method of fabricating contact holes on a semiconductor chip Aug 2, 2003 Issued
Array ( [id] => 7280922 [patent_doc_number] => 20040063299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => new [patent_app_number] => 10/630800 [patent_app_country] => US [patent_app_date] => 2003-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3926 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20040063299.pdf [firstpage_image] =>[orig_patent_app_number] => 10630800 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/630800
Semiconductor device and method for fabricating the same Jul 30, 2003 Issued
Array ( [id] => 988145 [patent_doc_number] => 06921700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-26 [patent_title] => 'Method of forming a transistor having multiple channels' [patent_app_type] => utility [patent_app_number] => 10/631093 [patent_app_country] => US [patent_app_date] => 2003-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4462 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/921/06921700.pdf [firstpage_image] =>[orig_patent_app_number] => 10631093 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/631093
Method of forming a transistor having multiple channels Jul 30, 2003 Issued
Array ( [id] => 975419 [patent_doc_number] => 06933181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-23 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/620430 [patent_app_country] => US [patent_app_date] => 2003-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 5254 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/933/06933181.pdf [firstpage_image] =>[orig_patent_app_number] => 10620430 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/620430
Method for fabricating semiconductor device Jul 16, 2003 Issued
Array ( [id] => 7400471 [patent_doc_number] => 20040023444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/614110 [patent_app_country] => US [patent_app_date] => 2003-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12118 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20040023444.pdf [firstpage_image] =>[orig_patent_app_number] => 10614110 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/614110
Method of manufacturing a semiconductor device Jul 7, 2003 Issued
Array ( [id] => 7433730 [patent_doc_number] => 20040002220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Method of purging semiconductor manufacturing apparatus and method of manufacturing semiconductor device' [patent_app_type] => new [patent_app_number] => 10/608020 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4979 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20040002220.pdf [firstpage_image] =>[orig_patent_app_number] => 10608020 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/608020
Method of purging semiconductor manufacturing apparatus and method of manufacturing semiconductor device Jun 29, 2003 Issued
Array ( [id] => 7221854 [patent_doc_number] => 20040072409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-15 [patent_title] => 'Coplanar integration of lattice-mismatched semiconductor with silicon via wafer bonding virtual substrates' [patent_app_type] => new [patent_app_number] => 10/603850 [patent_app_country] => US [patent_app_date] => 2003-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3482 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20040072409.pdf [firstpage_image] =>[orig_patent_app_number] => 10603850 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/603850
Coplanar integration of lattice-mismatched semiconductor with silicon via wafer bonding virtual substrates Jun 24, 2003 Issued
Array ( [id] => 1153343 [patent_doc_number] => 06770971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-03 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => B2 [patent_app_number] => 10/458920 [patent_app_country] => US [patent_app_date] => 2003-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 13004 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/770/06770971.pdf [firstpage_image] =>[orig_patent_app_number] => 10458920 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/458920
Semiconductor device and method of fabricating the same Jun 9, 2003 Issued
Array ( [id] => 7361659 [patent_doc_number] => 20040005118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-08 [patent_title] => 'Method of manufacturing tapered optical waveguide' [patent_app_type] => new [patent_app_number] => 10/453100 [patent_app_country] => US [patent_app_date] => 2003-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2489 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20040005118.pdf [firstpage_image] =>[orig_patent_app_number] => 10453100 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/453100
Method of manufacturing tapered optical waveguide Jun 2, 2003 Issued
Array ( [id] => 1073631 [patent_doc_number] => 06838296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-04 [patent_title] => 'Device and method for detecting alignment of deep trench capacitors and active areas in DRAM devices' [patent_app_type] => utility [patent_app_number] => 10/448920 [patent_app_country] => US [patent_app_date] => 2003-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 2894 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/838/06838296.pdf [firstpage_image] =>[orig_patent_app_number] => 10448920 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/448920
Device and method for detecting alignment of deep trench capacitors and active areas in DRAM devices May 28, 2003 Issued
10/432041 Alignment method in chip mounting device May 18, 2003 Abandoned
Array ( [id] => 1192920 [patent_doc_number] => 06730548 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Method of fabricating a thin film transistor' [patent_app_type] => B1 [patent_app_number] => 10/439720 [patent_app_country] => US [patent_app_date] => 2003-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 2535 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/730/06730548.pdf [firstpage_image] =>[orig_patent_app_number] => 10439720 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/439720
Method of fabricating a thin film transistor May 15, 2003 Issued
Array ( [id] => 1002342 [patent_doc_number] => 06908796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-21 [patent_title] => 'Method of manufacturing an electro-optical device' [patent_app_type] => utility [patent_app_number] => 10/420540 [patent_app_country] => US [patent_app_date] => 2003-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7317 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/908/06908796.pdf [firstpage_image] =>[orig_patent_app_number] => 10420540 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/420540
Method of manufacturing an electro-optical device Apr 20, 2003 Issued
Array ( [id] => 1146854 [patent_doc_number] => 06774059 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-10 [patent_title] => 'High crack resistance nitride process' [patent_app_type] => B1 [patent_app_number] => 10/417320 [patent_app_country] => US [patent_app_date] => 2003-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3938 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/774/06774059.pdf [firstpage_image] =>[orig_patent_app_number] => 10417320 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/417320
High crack resistance nitride process Apr 15, 2003 Issued
Array ( [id] => 1207010 [patent_doc_number] => 06717199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-06 [patent_title] => 'Tailored insulator properties for devices' [patent_app_type] => B2 [patent_app_number] => 10/408069 [patent_app_country] => US [patent_app_date] => 2003-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3992 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/717/06717199.pdf [firstpage_image] =>[orig_patent_app_number] => 10408069 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/408069
Tailored insulator properties for devices Apr 3, 2003 Issued
Array ( [id] => 1005372 [patent_doc_number] => 06905967 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-14 [patent_title] => 'Method for improving planarity of shallow trench isolation using multiple simultaneous tiling systems' [patent_app_type] => utility [patent_app_number] => 10/401400 [patent_app_country] => US [patent_app_date] => 2003-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 7844 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/905/06905967.pdf [firstpage_image] =>[orig_patent_app_number] => 10401400 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/401400
Method for improving planarity of shallow trench isolation using multiple simultaneous tiling systems Mar 30, 2003 Issued
Menu