Search

Belur V. Keshavan

Examiner (ID: 12700)

Most Active Art Unit
2825
Art Unit(s)
2825, 2823
Total Applications
284
Issued Applications
267
Pending Applications
6
Abandoned Applications
11

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17195854 [patent_doc_number] => 11164619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Distribution-following access operations for a memory device [patent_app_type] => utility [patent_app_number] => 16/544730 [patent_app_country] => US [patent_app_date] => 2019-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 21605 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16544730 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/544730
Distribution-following access operations for a memory device Aug 18, 2019 Issued
Array ( [id] => 15257545 [patent_doc_number] => 20190377506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => APPARATUSES AND METHODS TO CHANGE DATA CATEGORY VALUES [patent_app_type] => utility [patent_app_number] => 16/542827 [patent_app_country] => US [patent_app_date] => 2019-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23149 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16542827 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/542827
Apparatuses and methods to change data category values Aug 15, 2019 Issued
Array ( [id] => 15461455 [patent_doc_number] => 20200043552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => PROGRAMMABLE ARTIFICIAL NEURON AND ASSOCIATED PROGRAMMING METHOD [patent_app_type] => utility [patent_app_number] => 16/527974 [patent_app_country] => US [patent_app_date] => 2019-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5207 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16527974 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/527974
Programmable artificial neuron and associated programming method Jul 30, 2019 Issued
Array ( [id] => 16609069 [patent_doc_number] => 10910082 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-02 [patent_title] => Apparatus and method [patent_app_type] => utility [patent_app_number] => 16/527228 [patent_app_country] => US [patent_app_date] => 2019-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10621 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16527228 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/527228
Apparatus and method Jul 30, 2019 Issued
Array ( [id] => 16699703 [patent_doc_number] => 10950311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => Boosting read scheme with back-gate bias [patent_app_type] => utility [patent_app_number] => 16/456036 [patent_app_country] => US [patent_app_date] => 2019-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 30 [patent_no_of_words] => 15719 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16456036 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/456036
Boosting read scheme with back-gate bias Jun 27, 2019 Issued
Array ( [id] => 16544706 [patent_doc_number] => 20200411121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => MULTIDIMENSIONAL PSEUDORANDOM BINARY SEQUENCE ANALYSIS FOR A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/456522 [patent_app_country] => US [patent_app_date] => 2019-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16456522 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/456522
Multidimensional pseudorandom binary sequence analysis for a memory device Jun 27, 2019 Issued
Array ( [id] => 16447974 [patent_doc_number] => 10839905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Content addressable memory device having electrically floating body transistor [patent_app_type] => utility [patent_app_number] => 16/449820 [patent_app_country] => US [patent_app_date] => 2019-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 103 [patent_figures_cnt] => 139 [patent_no_of_words] => 29370 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16449820 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/449820
Content addressable memory device having electrically floating body transistor Jun 23, 2019 Issued
Array ( [id] => 14842605 [patent_doc_number] => 20190279703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => ADDRESS COUNTING CIRCUIT, MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/422629 [patent_app_country] => US [patent_app_date] => 2019-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11165 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16422629 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/422629
Address counting circuit, memory device and operating method thereof May 23, 2019 Issued
Array ( [id] => 15153881 [patent_doc_number] => 20190355418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => NON-CONTACT ELECTRON BEAM PROBING TECHNIQUES AND RELATED STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/419895 [patent_app_country] => US [patent_app_date] => 2019-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32830 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16419895 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/419895
Non-contact electron beam probing techniques and related structures May 21, 2019 Issued
Array ( [id] => 15984329 [patent_doc_number] => 10672500 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Non-contact measurement of memory cell threshold voltage [patent_app_type] => utility [patent_app_number] => 16/419885 [patent_app_country] => US [patent_app_date] => 2019-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 15869 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16419885 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/419885
Non-contact measurement of memory cell threshold voltage May 21, 2019 Issued
Array ( [id] => 16417611 [patent_doc_number] => 10825511 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Device, system, and method to change a consistency of behavior by a cell circuit [patent_app_type] => utility [patent_app_number] => 16/417538 [patent_app_country] => US [patent_app_date] => 2019-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13334 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16417538 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/417538
Device, system, and method to change a consistency of behavior by a cell circuit May 19, 2019 Issued
Array ( [id] => 16502265 [patent_doc_number] => 10867658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-15 [patent_title] => Address counting circuit, memory device and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/406849 [patent_app_country] => US [patent_app_date] => 2019-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11175 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16406849 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/406849
Address counting circuit, memory device and operating method thereof May 7, 2019 Issued
Array ( [id] => 15984241 [patent_doc_number] => 10672455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Method of self-testing and reusing of reference cells in a memory architecture [patent_app_type] => utility [patent_app_number] => 16/405701 [patent_app_country] => US [patent_app_date] => 2019-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4627 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16405701 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/405701
Method of self-testing and reusing of reference cells in a memory architecture May 6, 2019 Issued
Array ( [id] => 14676003 [patent_doc_number] => 20190237116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => STACK ACCESS CONTROL FOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/380285 [patent_app_country] => US [patent_app_date] => 2019-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16380285 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/380285
Stack access control for memory device Apr 9, 2019 Issued
Array ( [id] => 16293278 [patent_doc_number] => 10770131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => SRAM cell for interleaved wordline scheme [patent_app_type] => utility [patent_app_number] => 16/376198 [patent_app_country] => US [patent_app_date] => 2019-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7320 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16376198 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/376198
SRAM cell for interleaved wordline scheme Apr 4, 2019 Issued
Array ( [id] => 16347733 [patent_doc_number] => 20200312384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => APPARATUSES AND METHODS FOR COMPENSATION OF SENSE AMPLIFIERS [patent_app_type] => utility [patent_app_number] => 16/372000 [patent_app_country] => US [patent_app_date] => 2019-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7568 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16372000 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/372000
Apparatuses and methods for compensation of sense amplifiers Mar 31, 2019 Issued
Array ( [id] => 16347748 [patent_doc_number] => 20200312399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => PHASE CLOCK CORRECTION [patent_app_type] => utility [patent_app_number] => 16/371414 [patent_app_country] => US [patent_app_date] => 2019-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16328 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16371414 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/371414
Phase clock correction Mar 31, 2019 Issued
Array ( [id] => 16348352 [patent_doc_number] => 20200313003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => DEVICE, SYSTEM, AND METHOD TO CHANGE A CONSISTENCY OF BEHAVIOR BY A CELL CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/369856 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13258 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16369856 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/369856
Device, system, and method to change a consistency of behavior by a cell circuit Mar 28, 2019 Issued
Array ( [id] => 14630889 [patent_doc_number] => 20190228813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => REFRESH COMMAND CONTROL FOR HOST ASSIST OF ROW HAMMER MITIGATION [patent_app_type] => utility [patent_app_number] => 16/370578 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16210 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370578 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/370578
Refresh command control for host assist of row hammer mitigation Mar 28, 2019 Issued
Array ( [id] => 14572955 [patent_doc_number] => 20190214085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => MEMRISTIVE DOT PRODUCT ENGINE FOR VECTOR PROCESSING [patent_app_type] => utility [patent_app_number] => 16/353451 [patent_app_country] => US [patent_app_date] => 2019-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6455 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16353451 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/353451
Memristive dot product engine for vector processing Mar 13, 2019 Issued
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