Search

Belur V. Keshavan

Examiner (ID: 9359)

Most Active Art Unit
2825
Art Unit(s)
2823, 2825
Total Applications
284
Issued Applications
267
Pending Applications
6
Abandoned Applications
11

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6460232 [patent_doc_number] => 20020178312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Calculator capable of displaying processing status and stopping processing and method of the same' [patent_app_type] => new [patent_app_number] => 09/863326 [patent_app_country] => US [patent_app_date] => 2001-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1859 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20020178312.pdf [firstpage_image] =>[orig_patent_app_number] => 09863326 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/863326
Calculator capable of displaying processing status and stopping processing and method of the same May 23, 2001 Abandoned
Array ( [id] => 6899279 [patent_doc_number] => 20010047444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'Programmable throttle timer with fine resolution' [patent_app_type] => new [patent_app_number] => 09/829019 [patent_app_country] => US [patent_app_date] => 2001-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2280 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20010047444.pdf [firstpage_image] =>[orig_patent_app_number] => 09829019 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/829019
Programmable throttle circuit for each control device of a processing system Apr 8, 2001 Issued
Array ( [id] => 1154942 [patent_doc_number] => 06779066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-17 [patent_title] => 'Module having application-specific program stored therein' [patent_app_type] => B2 [patent_app_number] => 09/825927 [patent_app_country] => US [patent_app_date] => 2001-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3468 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/779/06779066.pdf [firstpage_image] =>[orig_patent_app_number] => 09825927 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/825927
Module having application-specific program stored therein Apr 4, 2001 Issued
09/743967 Communication method, communication system and electronic device Apr 4, 2001 Abandoned
Array ( [id] => 6636954 [patent_doc_number] => 20020016882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-07 [patent_title] => 'Digital device, data input-output control method, and data input-output control system' [patent_app_type] => new [patent_app_number] => 09/825284 [patent_app_country] => US [patent_app_date] => 2001-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8217 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20020016882.pdf [firstpage_image] =>[orig_patent_app_number] => 09825284 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/825284
Digital device, data input-output control method, and data input-output control system Apr 3, 2001 Abandoned
Array ( [id] => 1024786 [patent_doc_number] => 06889278 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-03 [patent_title] => 'Method and apparatus for fast acknowledgement and efficient servicing of interrupt sources coupled to high latency paths' [patent_app_type] => utility [patent_app_number] => 09/826271 [patent_app_country] => US [patent_app_date] => 2001-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6951 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/889/06889278.pdf [firstpage_image] =>[orig_patent_app_number] => 09826271 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/826271
Method and apparatus for fast acknowledgement and efficient servicing of interrupt sources coupled to high latency paths Apr 3, 2001 Issued
Array ( [id] => 1134014 [patent_doc_number] => 06792494 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-14 [patent_title] => 'Apparatus and method for parallel and serial PCI hot plug signals' [patent_app_type] => B2 [patent_app_number] => 09/821086 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3301 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/792/06792494.pdf [firstpage_image] =>[orig_patent_app_number] => 09821086 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/821086
Apparatus and method for parallel and serial PCI hot plug signals Mar 29, 2001 Issued
Array ( [id] => 5910500 [patent_doc_number] => 20020144037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'Data fetching mechanism and method for fetching data' [patent_app_type] => new [patent_app_number] => 09/819996 [patent_app_country] => US [patent_app_date] => 2001-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5445 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20020144037.pdf [firstpage_image] =>[orig_patent_app_number] => 09819996 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/819996
Data fetching mechanism and method for fetching data Mar 28, 2001 Abandoned
Array ( [id] => 6896713 [patent_doc_number] => 20010027503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Clock generator suitably interfacing with clocks having another frequency' [patent_app_type] => new [patent_app_number] => 09/815875 [patent_app_country] => US [patent_app_date] => 2001-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7204 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20010027503.pdf [firstpage_image] =>[orig_patent_app_number] => 09815875 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/815875
Clock generator suitably interfacing with clocks having another frequency Mar 21, 2001 Abandoned
Array ( [id] => 1214312 [patent_doc_number] => 06715019 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Bus reset management by a primary controller card of multiple controller cards' [patent_app_type] => B1 [patent_app_number] => 09/810963 [patent_app_country] => US [patent_app_date] => 2001-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9048 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/715/06715019.pdf [firstpage_image] =>[orig_patent_app_number] => 09810963 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/810963
Bus reset management by a primary controller card of multiple controller cards Mar 16, 2001 Issued
Array ( [id] => 5848342 [patent_doc_number] => 20020133659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'Carrying case for portable electronic devices' [patent_app_type] => new [patent_app_number] => 09/808349 [patent_app_country] => US [patent_app_date] => 2001-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2072 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20020133659.pdf [firstpage_image] =>[orig_patent_app_number] => 09808349 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/808349
Carrying case for portable electronic devices Mar 14, 2001 Issued
Array ( [id] => 7321090 [patent_doc_number] => 20040225774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'ENHANCING A PCI-X SPLIT COMPLETION TRANSACTION BY ALIGNING CACHELINES WITH AN ALLOWABLE DISCONNECT BOUNDARY\'S ENDING ADDRESS' [patent_app_type] => new [patent_app_number] => 09/792867 [patent_app_country] => US [patent_app_date] => 2001-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6222 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20040225774.pdf [firstpage_image] =>[orig_patent_app_number] => 09792867 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/792867
Enhancing a PCI-X split completion transaction by aligning cachelines with an allowable disconnect boundary's ending address Feb 22, 2001 Issued
Array ( [id] => 6889872 [patent_doc_number] => 20010025327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-27 [patent_title] => 'Information processing device, method thereof and recording medium' [patent_app_type] => new [patent_app_number] => 09/789154 [patent_app_country] => US [patent_app_date] => 2001-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3495 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20010025327.pdf [firstpage_image] =>[orig_patent_app_number] => 09789154 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/789154
Device and method for switching receiving/recording device in a broadcasting connection/point-to-point connection bus enviroment Feb 19, 2001 Issued
Array ( [id] => 6565268 [patent_doc_number] => 20020112108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-15 [patent_title] => 'Arrangement of circuit components for interfacing to a network' [patent_app_type] => new [patent_app_number] => 09/783805 [patent_app_country] => US [patent_app_date] => 2001-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1286 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20020112108.pdf [firstpage_image] =>[orig_patent_app_number] => 09783805 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/783805
Arrangement of circuit components for interfacing to a network Feb 14, 2001 Abandoned
Array ( [id] => 645477 [patent_doc_number] => 07124226 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Method or apparatus for establishing a plug and play (PnP) communication channel via an abstraction layer interface' [patent_app_type] => utility [patent_app_number] => 09/773202 [patent_app_country] => US [patent_app_date] => 2001-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3836 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/124/07124226.pdf [firstpage_image] =>[orig_patent_app_number] => 09773202 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/773202
Method or apparatus for establishing a plug and play (PnP) communication channel via an abstraction layer interface Jan 29, 2001 Issued
Array ( [id] => 7623867 [patent_doc_number] => 06725310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-20 [patent_title] => 'Scalable docking architecture to support various bandwidth' [patent_app_type] => B2 [patent_app_number] => 09/771047 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3216 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/725/06725310.pdf [firstpage_image] =>[orig_patent_app_number] => 09771047 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/771047
Scalable docking architecture to support various bandwidth Jan 25, 2001 Issued
Array ( [id] => 5990639 [patent_doc_number] => 20020099899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Bus isolation mechanism for sharing keyboard controller, super input output controller, and embedded controller devices' [patent_app_type] => new [patent_app_number] => 09/769913 [patent_app_country] => US [patent_app_date] => 2001-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3260 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20020099899.pdf [firstpage_image] =>[orig_patent_app_number] => 09769913 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/769913
Peripheral switching device with multiple sets of registers for supporting an ACPI full-operation state Jan 24, 2001 Issued
Array ( [id] => 5990615 [patent_doc_number] => 20020099892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Adaptive bus arbiter' [patent_app_type] => new [patent_app_number] => 09/727032 [patent_app_country] => US [patent_app_date] => 2000-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4444 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20020099892.pdf [firstpage_image] =>[orig_patent_app_number] => 09727032 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/727032
Bus access arbitration based on workload Nov 29, 2000 Issued
Array ( [id] => 6922100 [patent_doc_number] => 20010029560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-11 [patent_title] => 'Computer farm with a system for the hot insertion/extraction of processor cards' [patent_app_type] => new [patent_app_number] => 09/728362 [patent_app_country] => US [patent_app_date] => 2000-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2760 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20010029560.pdf [firstpage_image] =>[orig_patent_app_number] => 09728362 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/728362
Computer farm with a system for the hot insertion/extraction of processor cards Nov 29, 2000 Abandoned
Array ( [id] => 1183474 [patent_doc_number] => 06751697 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-15 [patent_title] => 'Method and system for a multi-phase net refresh on a bus bridge interconnect' [patent_app_type] => B1 [patent_app_number] => 09/724201 [patent_app_country] => US [patent_app_date] => 2000-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 10215 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751697.pdf [firstpage_image] =>[orig_patent_app_number] => 09724201 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/724201
Method and system for a multi-phase net refresh on a bus bridge interconnect Nov 26, 2000 Issued
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