Search

Belur V. Keshavan

Examiner (ID: 12700)

Most Active Art Unit
2825
Art Unit(s)
2825, 2823
Total Applications
284
Issued Applications
267
Pending Applications
6
Abandoned Applications
11

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16536246 [patent_doc_number] => 10878859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Utilizing write stream attributes in storage write commands [patent_app_type] => utility [patent_app_number] => 15/849014 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6853 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15849014 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/849014
Utilizing write stream attributes in storage write commands Dec 19, 2017 Issued
Array ( [id] => 14475135 [patent_doc_number] => 20190189214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => SYSTEM AND METHOD FOR MINIMIZING FLOATING GATE TO FLOATING GATE COUPLING EFFECTS DURING PROGRAMMING IN FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 15/849268 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3290 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15849268 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/849268
System and method for minimizing floating gate to floating gate coupling effects during programming in flash memory Dec 19, 2017 Issued
Array ( [id] => 15580187 [patent_doc_number] => 10580485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => System and method for adjusting read levels in a storage device based on bias functions [patent_app_type] => utility [patent_app_number] => 15/849572 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7482 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15849572 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/849572
System and method for adjusting read levels in a storage device based on bias functions Dec 19, 2017 Issued
Array ( [id] => 12649746 [patent_doc_number] => 20180108413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => Method for Managing a Fail Row of the Memory Plane of a Non Volatile Memory and Corresponding Memory Device [patent_app_type] => utility [patent_app_number] => 15/842476 [patent_app_country] => US [patent_app_date] => 2017-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3878 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15842476 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/842476
Method for managing a fail row of the memory plane of a non volatile memory and corresponding memory device Dec 13, 2017 Issued
Array ( [id] => 14413363 [patent_doc_number] => 20190172525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-06 [patent_title] => MEMORY WITH EXPANDABLE ROW WIDTH [patent_app_type] => utility [patent_app_number] => 15/830176 [patent_app_country] => US [patent_app_date] => 2017-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15830176 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/830176
Memory with expandable row width Dec 3, 2017 Issued
Array ( [id] => 14616571 [patent_doc_number] => 10360989 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Electronic device with a fuse-read trigger mechanism [patent_app_type] => utility [patent_app_number] => 15/830281 [patent_app_country] => US [patent_app_date] => 2017-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5247 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15830281 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/830281
Electronic device with a fuse-read trigger mechanism Dec 3, 2017 Issued
Array ( [id] => 15014747 [patent_doc_number] => 10453529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Resistive random access memory (RRAM) device, write verify method and reverse write verify method thereof [patent_app_type] => utility [patent_app_number] => 15/829987 [patent_app_country] => US [patent_app_date] => 2017-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3618 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15829987 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/829987
Resistive random access memory (RRAM) device, write verify method and reverse write verify method thereof Dec 3, 2017 Issued
Array ( [id] => 13875979 [patent_doc_number] => 20190034330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => MASS STORAGE DEVICE WITH DYNAMIC SINGLE LEVEL CELL (SLC) BUFFER SPECIFIC PROGRAM AND/OR ERASE SETTINGS [patent_app_type] => utility [patent_app_number] => 15/829764 [patent_app_country] => US [patent_app_date] => 2017-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15829764 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/829764
MASS STORAGE DEVICE WITH DYNAMIC SINGLE LEVEL CELL (SLC) BUFFER SPECIFIC PROGRAM AND/OR ERASE SETTINGS Nov 30, 2017 Abandoned
Array ( [id] => 13201099 [patent_doc_number] => 10115470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Circuit and method for biasing nonvolatile memory cells [patent_app_type] => utility [patent_app_number] => 15/804790 [patent_app_country] => US [patent_app_date] => 2017-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3209 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15804790 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/804790
Circuit and method for biasing nonvolatile memory cells Nov 5, 2017 Issued
Array ( [id] => 17121906 [patent_doc_number] => 11133046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => Data writing device for variable-resistance memory element and non-volatile flip-flop [patent_app_type] => utility [patent_app_number] => 16/339818 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11764 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16339818 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/339818
Data writing device for variable-resistance memory element and non-volatile flip-flop Oct 30, 2017 Issued
Array ( [id] => 15315011 [patent_doc_number] => 10522215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Reading circuit and method [patent_app_type] => utility [patent_app_number] => 15/797726 [patent_app_country] => US [patent_app_date] => 2017-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3642 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15797726 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/797726
Reading circuit and method Oct 29, 2017 Issued
Array ( [id] => 13201097 [patent_doc_number] => 10115469 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/796193 [patent_app_country] => US [patent_app_date] => 2017-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 63 [patent_no_of_words] => 20983 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15796193 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/796193
Semiconductor device Oct 26, 2017 Issued
Array ( [id] => 16495457 [patent_doc_number] => 10861504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Dynamic control of multi-region fabric [patent_app_type] => utility [patent_app_number] => 15/725912 [patent_app_country] => US [patent_app_date] => 2017-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5219 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15725912 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/725912
Dynamic control of multi-region fabric Oct 4, 2017 Issued
Array ( [id] => 14557699 [patent_doc_number] => 10347317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Method of self-testing and reusing of reference cells in a memory architecture [patent_app_type] => utility [patent_app_number] => 15/726084 [patent_app_country] => US [patent_app_date] => 2017-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4580 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726084 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/726084
Method of self-testing and reusing of reference cells in a memory architecture Oct 4, 2017 Issued
Array ( [id] => 13187675 [patent_doc_number] => 10109363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-23 [patent_title] => CMOS anti-fuse cell [patent_app_type] => utility [patent_app_number] => 15/707967 [patent_app_country] => US [patent_app_date] => 2017-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 5642 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15707967 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/707967
CMOS anti-fuse cell Sep 17, 2017 Issued
Array ( [id] => 13921127 [patent_doc_number] => 10204687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Semiconductor integrated circuit [patent_app_type] => utility [patent_app_number] => 15/703368 [patent_app_country] => US [patent_app_date] => 2017-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7184 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15703368 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/703368
Semiconductor integrated circuit Sep 12, 2017 Issued
Array ( [id] => 13282851 [patent_doc_number] => 10153016 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => Apparatus of offset voltage adjustment in input buffer [patent_app_type] => utility [patent_app_number] => 15/702848 [patent_app_country] => US [patent_app_date] => 2017-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6627 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15702848 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/702848
Apparatus of offset voltage adjustment in input buffer Sep 12, 2017 Issued
Array ( [id] => 13451287 [patent_doc_number] => 20180277186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/703340 [patent_app_country] => US [patent_app_date] => 2017-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15703340 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/703340
Memory device Sep 12, 2017 Issued
Array ( [id] => 12243044 [patent_doc_number] => 20180075908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/703078 [patent_app_country] => US [patent_app_date] => 2017-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7662 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15703078 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/703078
Semiconductor memory device Sep 12, 2017 Issued
Array ( [id] => 13434689 [patent_doc_number] => 20180268887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY [patent_app_type] => utility [patent_app_number] => 15/700592 [patent_app_country] => US [patent_app_date] => 2017-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6164 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15700592 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/700592
MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY Sep 10, 2017 Abandoned
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