Search

Belur V. Keshavan

Examiner (ID: 9359)

Most Active Art Unit
2825
Art Unit(s)
2823, 2825
Total Applications
284
Issued Applications
267
Pending Applications
6
Abandoned Applications
11

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1225510 [patent_doc_number] => 06704829 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Switch input processing module for switching signal transmission lines to transmit different types of signals' [patent_app_type] => B1 [patent_app_number] => 09/712384 [patent_app_country] => US [patent_app_date] => 2000-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8479 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/704/06704829.pdf [firstpage_image] =>[orig_patent_app_number] => 09712384 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/712384
Switch input processing module for switching signal transmission lines to transmit different types of signals Nov 12, 2000 Issued
Array ( [id] => 1186638 [patent_doc_number] => 06738845 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-18 [patent_title] => 'Bus architecture and shared bus arbitration method for a communication device' [patent_app_type] => B1 [patent_app_number] => 09/706577 [patent_app_country] => US [patent_app_date] => 2000-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5143 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/738/06738845.pdf [firstpage_image] =>[orig_patent_app_number] => 09706577 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/706577
Bus architecture and shared bus arbitration method for a communication device Nov 2, 2000 Issued
09/698033 Input devices for entering data into an electronic medical record (EMR) Oct 29, 2000 Abandoned
09/693688 System and a method for creating and accessing data Oct 19, 2000 Abandoned
Array ( [id] => 1218121 [patent_doc_number] => 06711646 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'Dual mode (registered/unbuffered) memory interface' [patent_app_type] => B1 [patent_app_number] => 09/693332 [patent_app_country] => US [patent_app_date] => 2000-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2783 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711646.pdf [firstpage_image] =>[orig_patent_app_number] => 09693332 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/693332
Dual mode (registered/unbuffered) memory interface Oct 19, 2000 Issued
Array ( [id] => 7630020 [patent_doc_number] => 06636919 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Method for host protection during hot swap in a bridged, pipelined network' [patent_app_type] => B1 [patent_app_number] => 09/690037 [patent_app_country] => US [patent_app_date] => 2000-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2900 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636919.pdf [firstpage_image] =>[orig_patent_app_number] => 09690037 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/690037
Method for host protection during hot swap in a bridged, pipelined network Oct 15, 2000 Issued
Array ( [id] => 1037090 [patent_doc_number] => 06877052 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-05 [patent_title] => 'System and method for improved half-duplex bus performance' [patent_app_type] => utility [patent_app_number] => 09/675991 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2968 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/877/06877052.pdf [firstpage_image] =>[orig_patent_app_number] => 09675991 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/675991
System and method for improved half-duplex bus performance Sep 28, 2000 Issued
Array ( [id] => 1336954 [patent_doc_number] => 06604160 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Computing system arbitrating and selectively providing resource-seeking tasks with takeaway of non-shareable resources' [patent_app_type] => B1 [patent_app_number] => 09/671971 [patent_app_country] => US [patent_app_date] => 2000-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7179 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/604/06604160.pdf [firstpage_image] =>[orig_patent_app_number] => 09671971 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/671971
Computing system arbitrating and selectively providing resource-seeking tasks with takeaway of non-shareable resources Sep 27, 2000 Issued
Array ( [id] => 1043145 [patent_doc_number] => 06871251 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-22 [patent_title] => 'High latency interface between hardware components' [patent_app_type] => utility [patent_app_number] => 09/661912 [patent_app_country] => US [patent_app_date] => 2000-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3319 [patent_no_of_claims] => 123 [patent_no_of_ind_claims] => 21 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/871/06871251.pdf [firstpage_image] =>[orig_patent_app_number] => 09661912 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/661912
High latency interface between hardware components Sep 13, 2000 Issued
Array ( [id] => 1210307 [patent_doc_number] => 06718413 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-06 [patent_title] => 'Contention-based methods for generating reduced number of interrupts' [patent_app_type] => B1 [patent_app_number] => 09/650774 [patent_app_country] => US [patent_app_date] => 2000-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7118 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/718/06718413.pdf [firstpage_image] =>[orig_patent_app_number] => 09650774 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/650774
Contention-based methods for generating reduced number of interrupts Aug 28, 2000 Issued
Array ( [id] => 1206828 [patent_doc_number] => 06721831 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-13 [patent_title] => 'Method for controlling bus in digital interface' [patent_app_type] => B1 [patent_app_number] => 09/644229 [patent_app_country] => US [patent_app_date] => 2000-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3306 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 512 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/721/06721831.pdf [firstpage_image] =>[orig_patent_app_number] => 09644229 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/644229
Method for controlling bus in digital interface Aug 22, 2000 Issued
09/639468 Fully programmable device operation control to allow commands Aug 15, 2000 Abandoned
Array ( [id] => 777821 [patent_doc_number] => 07003612 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-21 [patent_title] => 'PC switching device selectively switching between an input device and a plurality of computers having different electric power control mechanisms' [patent_app_type] => utility [patent_app_number] => 09/632587 [patent_app_country] => US [patent_app_date] => 2000-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 5824 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/003/07003612.pdf [firstpage_image] =>[orig_patent_app_number] => 09632587 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/632587
PC switching device selectively switching between an input device and a plurality of computers having different electric power control mechanisms Aug 3, 2000 Issued
Array ( [id] => 7633101 [patent_doc_number] => 06658519 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Bus bridge with embedded input/output (I/O) and transaction tracing capabilities' [patent_app_type] => B1 [patent_app_number] => 09/627503 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5101 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658519.pdf [firstpage_image] =>[orig_patent_app_number] => 09627503 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/627503
Bus bridge with embedded input/output (I/O) and transaction tracing capabilities Jul 27, 2000 Issued
Array ( [id] => 1183445 [patent_doc_number] => 06751692 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-15 [patent_title] => 'Adapter for memory device and connecting method using the same' [patent_app_type] => B1 [patent_app_number] => 09/627072 [patent_app_country] => US [patent_app_date] => 2000-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 5894 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751692.pdf [firstpage_image] =>[orig_patent_app_number] => 09627072 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/627072
Adapter for memory device and connecting method using the same Jul 26, 2000 Issued
Array ( [id] => 1177382 [patent_doc_number] => 06760797 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-06 [patent_title] => 'Method for allocating channel in device having digital interface' [patent_app_type] => B1 [patent_app_number] => 09/626244 [patent_app_country] => US [patent_app_date] => 2000-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2497 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/760/06760797.pdf [firstpage_image] =>[orig_patent_app_number] => 09626244 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/626244
Method for allocating channel in device having digital interface Jul 25, 2000 Issued
Array ( [id] => 1225440 [patent_doc_number] => 06704816 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Method and apparatus for executing standard functions in a computer system using a field programmable gate array' [patent_app_type] => B1 [patent_app_number] => 09/625579 [patent_app_country] => US [patent_app_date] => 2000-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6274 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/704/06704816.pdf [firstpage_image] =>[orig_patent_app_number] => 09625579 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/625579
Method and apparatus for executing standard functions in a computer system using a field programmable gate array Jul 24, 2000 Issued
Array ( [id] => 1225474 [patent_doc_number] => 06704824 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Universal serial bus adapter with automatic installation' [patent_app_type] => B1 [patent_app_number] => 09/619958 [patent_app_country] => US [patent_app_date] => 2000-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2916 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/704/06704824.pdf [firstpage_image] =>[orig_patent_app_number] => 09619958 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/619958
Universal serial bus adapter with automatic installation Jul 19, 2000 Issued
Array ( [id] => 1329010 [patent_doc_number] => 06606675 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-12 [patent_title] => 'Clock synchronization in systems with multi-channel high-speed bus subsystems' [patent_app_type] => B1 [patent_app_number] => 09/620332 [patent_app_country] => US [patent_app_date] => 2000-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3731 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/606/06606675.pdf [firstpage_image] =>[orig_patent_app_number] => 09620332 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/620332
Clock synchronization in systems with multi-channel high-speed bus subsystems Jul 19, 2000 Issued
Array ( [id] => 1186649 [patent_doc_number] => 06738856 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-18 [patent_title] => 'External display peripheral for coupling to a universal serial bus port or hub on a computer' [patent_app_type] => B1 [patent_app_number] => 09/618680 [patent_app_country] => US [patent_app_date] => 2000-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6140 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/738/06738856.pdf [firstpage_image] =>[orig_patent_app_number] => 09618680 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/618680
External display peripheral for coupling to a universal serial bus port or hub on a computer Jul 18, 2000 Issued
Menu