Search

Belur V. Keshavan

Examiner (ID: 18924)

Most Active Art Unit
2825
Art Unit(s)
2823, 2825
Total Applications
284
Issued Applications
267
Pending Applications
6
Abandoned Applications
11

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7358715 [patent_doc_number] => 20040004597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-08 [patent_title] => 'Capacitor structure in a low temperature poly silicon display' [patent_app_type] => new [patent_app_number] => 10/251710 [patent_app_country] => US [patent_app_date] => 2002-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1748 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20040004597.pdf [firstpage_image] =>[orig_patent_app_number] => 10251710 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/251710
Capacitor structure in a low temperature poly silicon display Sep 20, 2002 Abandoned
Array ( [id] => 6817884 [patent_doc_number] => 20030068842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-10 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/242720 [patent_app_country] => US [patent_app_date] => 2002-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4835 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20030068842.pdf [firstpage_image] =>[orig_patent_app_number] => 10242720 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/242720
Method of manufacturing a semiconductor device Sep 12, 2002 Issued
Array ( [id] => 1239718 [patent_doc_number] => 06686281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-03 [patent_title] => 'Method for fabricating a semiconductor device and a substrate processing apparatus' [patent_app_type] => B2 [patent_app_number] => 10/234520 [patent_app_country] => US [patent_app_date] => 2002-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4068 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/686/06686281.pdf [firstpage_image] =>[orig_patent_app_number] => 10234520 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/234520
Method for fabricating a semiconductor device and a substrate processing apparatus Sep 4, 2002 Issued
Array ( [id] => 6720574 [patent_doc_number] => 20030054262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'In-situ balancing for phase-shifting mask' [patent_app_type] => new [patent_app_number] => 10/231520 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4411 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20030054262.pdf [firstpage_image] =>[orig_patent_app_number] => 10231520 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/231520
In-situ balancing for phase-shifting mask Aug 28, 2002 Issued
Array ( [id] => 1141596 [patent_doc_number] => 06777331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-17 [patent_title] => 'Multilayered copper structure for improving adhesion property' [patent_app_type] => B2 [patent_app_number] => 10/225920 [patent_app_country] => US [patent_app_date] => 2002-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5391 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/777/06777331.pdf [firstpage_image] =>[orig_patent_app_number] => 10225920 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/225920
Multilayered copper structure for improving adhesion property Aug 22, 2002 Issued
Array ( [id] => 1223656 [patent_doc_number] => 06699741 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-02 [patent_title] => 'Single poly bipolar transistor and method that uses a selectively epitaxially grown highly-boron-doped silicon layer as a diffusion source for an extrinsic base region' [patent_app_type] => B1 [patent_app_number] => 10/222620 [patent_app_country] => US [patent_app_date] => 2002-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 3652 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/699/06699741.pdf [firstpage_image] =>[orig_patent_app_number] => 10222620 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/222620
Single poly bipolar transistor and method that uses a selectively epitaxially grown highly-boron-doped silicon layer as a diffusion source for an extrinsic base region Aug 15, 2002 Issued
Array ( [id] => 7313682 [patent_doc_number] => 20040033695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-19 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => new [patent_app_number] => 10/216720 [patent_app_country] => US [patent_app_date] => 2002-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1802 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20040033695.pdf [firstpage_image] =>[orig_patent_app_number] => 10216720 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/216720
Method for manufacturing semiconductor device Aug 12, 2002 Issued
Array ( [id] => 1205450 [patent_doc_number] => 06716672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-06 [patent_title] => 'Three dimensional interconnection method and electronic device obtained by same' [patent_app_type] => B2 [patent_app_number] => 10/182720 [patent_app_country] => US [patent_app_date] => 2002-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2661 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/716/06716672.pdf [firstpage_image] =>[orig_patent_app_number] => 10182720 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/182720
Three dimensional interconnection method and electronic device obtained by same Aug 8, 2002 Issued
Array ( [id] => 1062754 [patent_doc_number] => 06849498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-01 [patent_title] => 'Method of manufacturing semiconductor capacitor' [patent_app_type] => utility [patent_app_number] => 10/212878 [patent_app_country] => US [patent_app_date] => 2002-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 5268 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/849/06849498.pdf [firstpage_image] =>[orig_patent_app_number] => 10212878 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/212878
Method of manufacturing semiconductor capacitor Aug 6, 2002 Issued
Array ( [id] => 6447024 [patent_doc_number] => 20020177259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Method of fabricating a liquid crystal display' [patent_app_type] => new [patent_app_number] => 10/196415 [patent_app_country] => US [patent_app_date] => 2002-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3030 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20020177259.pdf [firstpage_image] =>[orig_patent_app_number] => 10196415 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/196415
Method of fabricating a liquid crystal display Jul 16, 2002 Issued
Array ( [id] => 1248137 [patent_doc_number] => 06673640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-06 [patent_title] => 'Method of manufacturing semiconductor device for evaluation capable of evaluating crystal defect using in-line test by avoiding using preferential etching process' [patent_app_type] => B2 [patent_app_number] => 10/191320 [patent_app_country] => US [patent_app_date] => 2002-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 38 [patent_no_of_words] => 9120 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/673/06673640.pdf [firstpage_image] =>[orig_patent_app_number] => 10191320 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/191320
Method of manufacturing semiconductor device for evaluation capable of evaluating crystal defect using in-line test by avoiding using preferential etching process Jul 9, 2002 Issued
Array ( [id] => 1284526 [patent_doc_number] => 06642592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-04 [patent_title] => 'Semiconductor device and method for fabricating same' [patent_app_type] => B2 [patent_app_number] => 10/184991 [patent_app_country] => US [patent_app_date] => 2002-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 24 [patent_no_of_words] => 3178 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/642/06642592.pdf [firstpage_image] =>[orig_patent_app_number] => 10184991 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/184991
Semiconductor device and method for fabricating same Jun 30, 2002 Issued
Array ( [id] => 1261443 [patent_doc_number] => 06664154 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Method of using amorphous carbon film as a sacrificial layer in replacement gate integration processes' [patent_app_type] => B1 [patent_app_number] => 10/185320 [patent_app_country] => US [patent_app_date] => 2002-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2417 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/664/06664154.pdf [firstpage_image] =>[orig_patent_app_number] => 10185320 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/185320
Method of using amorphous carbon film as a sacrificial layer in replacement gate integration processes Jun 27, 2002 Issued
Array ( [id] => 6805066 [patent_doc_number] => 20030232460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-18 [patent_title] => 'SEMICONDUCTOR DEVICES INCLUDING PERIPHERALLY LOCATED BOND PADS, ASSEMBLIES, PACKAGES, AND METHODS' [patent_app_type] => new [patent_app_number] => 10/183820 [patent_app_country] => US [patent_app_date] => 2002-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7719 [patent_no_of_claims] => 77 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20030232460.pdf [firstpage_image] =>[orig_patent_app_number] => 10183820 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/183820
Semiconductor devices including peripherally located bond pads, assemblies, packages, and methods Jun 26, 2002 Issued
Array ( [id] => 1306582 [patent_doc_number] => 06617210 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-09 [patent_title] => 'Method for making a semiconductor device having a high-k gate dielectric' [patent_app_type] => B1 [patent_app_number] => 10/159520 [patent_app_country] => US [patent_app_date] => 2002-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1463 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/617/06617210.pdf [firstpage_image] =>[orig_patent_app_number] => 10159520 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/159520
Method for making a semiconductor device having a high-k gate dielectric May 30, 2002 Issued
Array ( [id] => 1288775 [patent_doc_number] => 06632723 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-14 [patent_title] => 'Semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/132520 [patent_app_country] => US [patent_app_date] => 2002-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 66 [patent_no_of_words] => 14190 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/632/06632723.pdf [firstpage_image] =>[orig_patent_app_number] => 10132520 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/132520
Semiconductor device Apr 25, 2002 Issued
Array ( [id] => 6547710 [patent_doc_number] => 20020110977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-15 [patent_title] => 'Semiconductor device having concave electrode and convex electrode and method of manufacturing thereof' [patent_app_type] => new [patent_app_number] => 10/119023 [patent_app_country] => US [patent_app_date] => 2002-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4461 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20020110977.pdf [firstpage_image] =>[orig_patent_app_number] => 10119023 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/119023
Semiconductor device having concave electrode and convex electrode and method of manufacturing thereof Apr 9, 2002 Issued
Array ( [id] => 1420441 [patent_doc_number] => 06512265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-28 [patent_title] => 'Method of fabricating semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/106364 [patent_app_country] => US [patent_app_date] => 2002-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 9344 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/512/06512265.pdf [firstpage_image] =>[orig_patent_app_number] => 10106364 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/106364
Method of fabricating semiconductor device Mar 26, 2002 Issued
Array ( [id] => 1299595 [patent_doc_number] => 06624032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-23 [patent_title] => 'Structure and process flow for fabrication of dual gate floating body integrated MOS transistors' [patent_app_type] => B2 [patent_app_number] => 10/102319 [patent_app_country] => US [patent_app_date] => 2002-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 44 [patent_no_of_words] => 3557 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/624/06624032.pdf [firstpage_image] =>[orig_patent_app_number] => 10102319 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/102319
Structure and process flow for fabrication of dual gate floating body integrated MOS transistors Mar 19, 2002 Issued
Array ( [id] => 1043717 [patent_doc_number] => 06867150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-15 [patent_title] => 'Ozone treatment method and ozone treatment apparatus' [patent_app_type] => utility [patent_app_number] => 10/312560 [patent_app_country] => US [patent_app_date] => 2002-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3719 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/867/06867150.pdf [firstpage_image] =>[orig_patent_app_number] => 10312560 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/312560
Ozone treatment method and ozone treatment apparatus Mar 17, 2002 Issued
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