
Belur V. Keshavan
Examiner (ID: 18924)
| Most Active Art Unit | 2825 |
| Art Unit(s) | 2823, 2825 |
| Total Applications | 284 |
| Issued Applications | 267 |
| Pending Applications | 6 |
| Abandoned Applications | 11 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1015012
[patent_doc_number] => 06894356
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-17
[patent_title] => 'SRAM system having very lightly doped SRAM load transistors for improving SRAM cell stability and method for making the same'
[patent_app_type] => utility
[patent_app_number] => 10/099520
[patent_app_country] => US
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/894/06894356.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/099520 | SRAM system having very lightly doped SRAM load transistors for improving SRAM cell stability and method for making the same | Mar 14, 2002 | Issued |
Array
(
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[patent_doc_number] => 20020130271
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[patent_kind] => A1
[patent_issue_date] => 2002-09-19
[patent_title] => 'Ion implantation method and ion implantation equipment'
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[patent_app_country] => US
[patent_app_date] => 2002-02-22
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Array
(
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[patent_doc_number] => 06759304
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-07-06
[patent_title] => 'DRAM memory integration method'
[patent_app_type] => B2
[patent_app_number] => 10/042520
[patent_app_country] => US
[patent_app_date] => 2002-01-09
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/042520 | DRAM memory integration method | Jan 8, 2002 | Issued |
Array
(
[id] => 6683373
[patent_doc_number] => 20030119237
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-26
[patent_title] => 'CMOS vertical replacement gate (VRG) transistors'
[patent_app_type] => new
[patent_app_number] => 10/036020
[patent_app_country] => US
[patent_app_date] => 2001-12-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0119/20030119237.pdf
[firstpage_image] =>[orig_patent_app_number] => 10036020
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/036020 | CMOS vertical replacement gate (VRG) transistors | Dec 25, 2001 | Issued |
Array
(
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[patent_doc_number] => 20020034868
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-03-21
[patent_title] => 'Semiconductor device having a gate and fabrication method therefor'
[patent_app_type] => new
[patent_app_number] => 09/998131
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/998131 | Semiconductor device having a gate and fabrication method therefor | Dec 2, 2001 | Abandoned |
Array
(
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[patent_issue_date] => 2003-12-23
[patent_title] => 'Semiconductor device and method of fabricating the same'
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Array
(
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[patent_doc_number] => 06528434
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[patent_issue_date] => 2003-03-04
[patent_title] => 'Method of forming a silicon oxide layer using pulsed nitrogen plasma implantation'
[patent_app_type] => B2
[patent_app_number] => 09/682810
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Array
(
[id] => 6028691
[patent_doc_number] => 20020017665
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[patent_issue_date] => 2002-02-14
[patent_title] => 'Thin film transistor and method of manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 09/978050
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Array
(
[id] => 6459096
[patent_doc_number] => 20020020872
[patent_country] => US
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[patent_issue_date] => 2002-02-21
[patent_title] => 'Memory cell of the EEPROM type having its threshold adjusted by implantation'
[patent_app_type] => new
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/976484 | Memory cell of the EEPROM type having its threshold adjusted by implantation | Oct 11, 2001 | Abandoned |
Array
(
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[patent_title] => 'Semiconductor light-emitting device and method of manufacturing the same'
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Array
(
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[patent_title] => 'Method of fabricating a semiconductor device using a damascene metal gate'
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Array
(
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[patent_title] => 'Methods and systems for forming embedded DRAM for an MIM capacitor'
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Array
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Array
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Array
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Array
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Array
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