
Belur V. Keshavan
Examiner (ID: 2641)
| Most Active Art Unit | 2825 |
| Art Unit(s) | 2825, 2823 |
| Total Applications | 284 |
| Issued Applications | 267 |
| Pending Applications | 6 |
| Abandoned Applications | 11 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1436623
[patent_doc_number] => 06355974
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-12
[patent_title] => 'Method to prevent the formation of a thinner portion of insulating layer at the junction between the side walls and the bottom insulator'
[patent_app_type] => B1
[patent_app_number] => 09/588110
[patent_app_country] => US
[patent_app_date] => 2000-05-31
[patent_effective_date] => 0000-00-00
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[patent_words_short_claim] => 42
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/355/06355974.pdf
[firstpage_image] =>[orig_patent_app_number] => 09588110
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/588110 | Method to prevent the formation of a thinner portion of insulating layer at the junction between the side walls and the bottom insulator | May 30, 2000 | Issued |
Array
(
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[patent_doc_number] => 06429043
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-06
[patent_title] => 'Semiconductor circuitry device and method for manufacturing the same'
[patent_app_type] => B1
[patent_app_number] => 09/566390
[patent_app_country] => US
[patent_app_date] => 2000-05-08
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[pdf_file] => patents/06/429/06429043.pdf
[firstpage_image] =>[orig_patent_app_number] => 09566390
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/566390 | Semiconductor circuitry device and method for manufacturing the same | May 7, 2000 | Issued |
Array
(
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[patent_doc_number] => 06518153
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-11
[patent_title] => 'Method for making gate electrodes of low sheet resistance for embedded dynamic random access memory devices'
[patent_app_type] => B1
[patent_app_number] => 09/562911
[patent_app_country] => US
[patent_app_date] => 2000-05-02
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[pdf_file] => patents/06/518/06518153.pdf
[firstpage_image] =>[orig_patent_app_number] => 09562911
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/562911 | Method for making gate electrodes of low sheet resistance for embedded dynamic random access memory devices | May 1, 2000 | Issued |
Array
(
[id] => 1367500
[patent_doc_number] => 06566236
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-20
[patent_title] => 'Gate structures with increased etch margin for self-aligned contact and the method of forming the same'
[patent_app_type] => B1
[patent_app_number] => 09/558941
[patent_app_country] => US
[patent_app_date] => 2000-04-26
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 09558941
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/558941 | Gate structures with increased etch margin for self-aligned contact and the method of forming the same | Apr 25, 2000 | Issued |
Array
(
[id] => 1561047
[patent_doc_number] => 06362030
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-26
[patent_title] => 'Method of manufacturing an active matrix substrate'
[patent_app_type] => B1
[patent_app_number] => 09/553031
[patent_app_country] => US
[patent_app_date] => 2000-04-20
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 09553031
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/553031 | Method of manufacturing an active matrix substrate | Apr 19, 2000 | Issued |
Array
(
[id] => 4328567
[patent_doc_number] => 06312967
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-06
[patent_title] => 'Semiconductor device and manufacture method thereof, as well as light emitting semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/553519
[patent_app_country] => US
[patent_app_date] => 2000-04-20
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[pdf_file] => patents/06/312/06312967.pdf
[firstpage_image] =>[orig_patent_app_number] => 553519
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/553519 | Semiconductor device and manufacture method thereof, as well as light emitting semiconductor device | Apr 19, 2000 | Issued |
Array
(
[id] => 1474581
[patent_doc_number] => 06387779
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-14
[patent_title] => 'Method of crystallizing a silicon film and thin film transistor and fabricating method thereof using the same'
[patent_app_type] => B1
[patent_app_number] => 09/549521
[patent_app_country] => US
[patent_app_date] => 2000-04-14
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/387/06387779.pdf
[firstpage_image] =>[orig_patent_app_number] => 09549521
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/549521 | Method of crystallizing a silicon film and thin film transistor and fabricating method thereof using the same | Apr 13, 2000 | Issued |
Array
(
[id] => 1382011
[patent_doc_number] => 06551900
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-22
[patent_title] => 'Trench gate oxide formation method'
[patent_app_type] => B1
[patent_app_number] => 09/547730
[patent_app_country] => US
[patent_app_date] => 2000-04-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/551/06551900.pdf
[firstpage_image] =>[orig_patent_app_number] => 09547730
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/547730 | Trench gate oxide formation method | Apr 11, 2000 | Issued |
Array
(
[id] => 7640331
[patent_doc_number] => 06395583
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-28
[patent_title] => 'Semiconductor device with a coating of Pb-free Sn-base solder and manufacturing method therefor'
[patent_app_type] => B1
[patent_app_number] => 09/548351
[patent_app_country] => US
[patent_app_date] => 2000-04-12
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[patent_drawing_sheets_cnt] => 3
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[firstpage_image] =>[orig_patent_app_number] => 09548351
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/548351 | Semiconductor device with a coating of Pb-free Sn-base solder and manufacturing method therefor | Apr 11, 2000 | Issued |
Array
(
[id] => 4271885
[patent_doc_number] => 06323143
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-27
[patent_title] => 'Method for making silicon nitride-oxide ultra-thin gate insulating layers for submicrometer field effect transistors'
[patent_app_type] => 1
[patent_app_number] => 9/534161
[patent_app_country] => US
[patent_app_date] => 2000-03-24
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 3144
[patent_no_of_claims] => 22
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[pdf_file] => patents/06/323/06323143.pdf
[firstpage_image] =>[orig_patent_app_number] => 534161
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/534161 | Method for making silicon nitride-oxide ultra-thin gate insulating layers for submicrometer field effect transistors | Mar 23, 2000 | Issued |
Array
(
[id] => 1532433
[patent_doc_number] => 06410383
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-25
[patent_title] => 'Method of forming conducting diffusion barriers'
[patent_app_type] => B1
[patent_app_number] => 09/527541
[patent_app_country] => US
[patent_app_date] => 2000-03-16
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[pdf_file] => patents/06/410/06410383.pdf
[firstpage_image] =>[orig_patent_app_number] => 09527541
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/527541 | Method of forming conducting diffusion barriers | Mar 15, 2000 | Issued |
Array
(
[id] => 1414932
[patent_doc_number] => 06511859
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-01-28
[patent_title] => 'IC-compatible parylene MEMS technology and its application in integrated sensors'
[patent_app_type] => B1
[patent_app_number] => 09/523399
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[pdf_file] => patents/06/511/06511859.pdf
[firstpage_image] =>[orig_patent_app_number] => 09523399
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/523399 | IC-compatible parylene MEMS technology and its application in integrated sensors | Mar 9, 2000 | Issued |
Array
(
[id] => 1419171
[patent_doc_number] => 06506655
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[patent_issue_date] => 2003-01-14
[patent_title] => 'Bipolar transistor manufacturing method'
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[patent_app_number] => 09/517241
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[firstpage_image] =>[orig_patent_app_number] => 09517241
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/517241 | Bipolar transistor manufacturing method | Mar 1, 2000 | Issued |
Array
(
[id] => 1494951
[patent_doc_number] => 06403452
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[patent_kind] => B1
[patent_issue_date] => 2002-06-11
[patent_title] => 'Ion implantation method and ion implantation equipment'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/510240 | Ion implantation method and ion implantation equipment | Feb 21, 2000 | Issued |
Array
(
[id] => 1561061
[patent_doc_number] => 06362035
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[patent_title] => 'Channel stop ion implantation method for CMOS integrated circuits'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/498741 | Channel stop ion implantation method for CMOS integrated circuits | Feb 6, 2000 | Issued |
| 09/498740 | New method to prevent side damage of metal during via etch | Feb 6, 2000 | Abandoned |
Array
(
[id] => 1359072
[patent_doc_number] => 06573179
[patent_country] => US
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[patent_issue_date] => 2003-06-03
[patent_title] => 'Forming a strong interface between interconnect and encapsulation to minimize electromigration'
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[patent_app_number] => 09/496223
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/496223 | Forming a strong interface between interconnect and encapsulation to minimize electromigration | Jan 31, 2000 | Issued |
Array
(
[id] => 4325412
[patent_doc_number] => 06329291
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[patent_issue_date] => 2001-12-11
[patent_title] => 'Method of forming a lower storage node of a capacitor for dynamic random access memory'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/493671 | Method of forming a lower storage node of a capacitor for dynamic random access memory | Jan 27, 2000 | Issued |
Array
(
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[patent_issue_date] => 2000-11-07
[patent_title] => 'On-chip ESD protection in dual voltage CMOS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/491604 | On-chip ESD protection in dual voltage CMOS | Jan 25, 2000 | Issued |
Array
(
[id] => 1399262
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[patent_issue_date] => 2003-03-25
[patent_title] => 'Method of forming a via hole in a semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/489890 | Method of forming a via hole in a semiconductor device | Jan 23, 2000 | Issued |