Ben Lewis

Array ( [id] => 18680145 [patent_doc_number] => 20230317803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => TRANSISTOR BACKSIDE ROUTING LAYERS WITH CONTACTS HAVING VARYING DEPTHS [patent_app_type] => utility [patent_app_number] => 17/710873 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7928 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17710873 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20675325 [patent_doc_number] => 12615859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-28 [patent_title] => Photo-detecting apparatus [patent_app_type] => utility [patent_app_number] => 17/699546 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 31 [patent_no_of_words] => 11087 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17699546 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19191594 [patent_doc_number] => 20240170507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => IMAGING DEVICE AND MANUFACTURING METHOD FOR IMAGING DEVICE [patent_app_type] => utility [patent_app_number] => 18/551613 [patent_app_country] => US [patent_app_date] => 2022-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12840 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18551613 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17564550 [patent_doc_number] => 20220128699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => LIDAR SYSTEMS FOR PHONES [patent_app_type] => utility [patent_app_number] => 17/571989 [patent_app_country] => US [patent_app_date] => 2022-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7701 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17571989 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18473367 [patent_doc_number] => 20230207655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => FORMATION OF METAL CONTACTS TO SILICON GERMANIUM LAYERS WITH ETCH RESISTIVE CAP LAYERS [patent_app_type] => utility [patent_app_number] => 17/561915 [patent_app_country] => US [patent_app_date] => 2021-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15343 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561915 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18456230 [patent_doc_number] => 20230197512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => INTERCONNECT LINE STRUCTURES WITH METAL CHALCOGENIDE CAP MATERIALS [patent_app_type] => utility [patent_app_number] => 17/560089 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7564 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17560089 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18456554 [patent_doc_number] => 20230197836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => INTEGRATED CIRCUITS WITH MAX OR MX CONDUCTIVE MATERIALS [patent_app_type] => utility [patent_app_number] => 17/557128 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19577 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17557128 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20259059 [patent_doc_number] => 12431424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Buried power rails integrated with decoupling capacitance [patent_app_type] => utility [patent_app_number] => 17/554112 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 14569 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17554112 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18456543 [patent_doc_number] => 20230197825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => CONTACTS WITH INTERFACE FERMI LEVEL TUNING LAYERS [patent_app_type] => utility [patent_app_number] => 17/555247 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16461 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17555247 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20553007 [patent_doc_number] => 12563817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Integrating gate-cuts and single diffusion break isolation post-RMG using low-temperature protective liners [patent_app_type] => utility [patent_app_number] => 17/545013 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2268 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17545013 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20347550 [patent_doc_number] => 12471288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Three-dimensional nanoribbon-based hysteretic memory [patent_app_type] => utility [patent_app_number] => 17/543809 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 15514 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17543809 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18365908 [patent_doc_number] => 20230147499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => ENRICHED SEMICONDUCTOR NANORIBBONS FOR PRODUCING INTRINSIC COMPRESSIVE STRAIN [patent_app_type] => utility [patent_app_number] => 17/523710 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17523710 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18540813 [patent_doc_number] => 20230245924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => SELECTIVE DEPOSITION USING GRAPHENE AS AN INHIBITOR [patent_app_type] => utility [patent_app_number] => 18/002043 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19886 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18002043 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18379665 [patent_doc_number] => 20230154754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => LOSS PREVENTION DURING ATOMIC LAYER DEPOSITION [patent_app_type] => utility [patent_app_number] => 17/995461 [patent_app_country] => US [patent_app_date] => 2021-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8921 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17995461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20145456 [patent_doc_number] => 12379798 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Display assembly, display apparatus, and driving method [patent_app_type] => utility [patent_app_number] => 17/915920 [patent_app_country] => US [patent_app_date] => 2021-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 7525 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17915920 [rel_patent_id] =>[rel_patent_doc_number] =>)