Search

Ben M. Rifkin

Examiner (ID: 13211, Phone: (571)272-9768 , Office: P/2122 )

Most Active Art Unit
2122
Art Unit(s)
2122, 2129, 2198, 2124, 2123
Total Applications
534
Issued Applications
224
Pending Applications
86
Abandoned Applications
235

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5499848 [patent_doc_number] => 20090160536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-25 [patent_title] => 'ELECTRONIC DEVICE, LOAD FLUCTUATION COMPENSATION CIRCUIT, POWER SUPPLY, AND TEST APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/049394 [patent_app_country] => US [patent_app_date] => 2008-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9923 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20090160536.pdf [firstpage_image] =>[orig_patent_app_number] => 12049394 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/049394
Electronic device, load fluctuation compensation circuit, power supply, and test apparatus Mar 16, 2008 Issued
Array ( [id] => 5328385 [patent_doc_number] => 20090108862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'Testing system module' [patent_app_type] => utility [patent_app_number] => 12/045711 [patent_app_country] => US [patent_app_date] => 2008-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2252 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20090108862.pdf [firstpage_image] =>[orig_patent_app_number] => 12045711 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/045711
Testing system module Mar 10, 2008 Abandoned
Array ( [id] => 4466188 [patent_doc_number] => 07936177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-03 [patent_title] => 'Providing an electrically conductive wall structure adjacent a contact structure of an electronic device' [patent_app_type] => utility [patent_app_number] => 12/044893 [patent_app_country] => US [patent_app_date] => 2008-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 13571 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/936/07936177.pdf [firstpage_image] =>[orig_patent_app_number] => 12044893 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/044893
Providing an electrically conductive wall structure adjacent a contact structure of an electronic device Mar 6, 2008 Issued
Array ( [id] => 349338 [patent_doc_number] => 07495457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-24 [patent_title] => 'Semiconductor device evaluation method and apparatus using the same' [patent_app_type] => utility [patent_app_number] => 12/042195 [patent_app_country] => US [patent_app_date] => 2008-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6901 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/495/07495457.pdf [firstpage_image] =>[orig_patent_app_number] => 12042195 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/042195
Semiconductor device evaluation method and apparatus using the same Mar 3, 2008 Issued
Array ( [id] => 4815896 [patent_doc_number] => 20080223155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'Probe assembly for lapping bar using patterned probe' [patent_app_type] => utility [patent_app_number] => 12/073174 [patent_app_country] => US [patent_app_date] => 2008-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4913 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20080223155.pdf [firstpage_image] =>[orig_patent_app_number] => 12073174 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/073174
Probe assembly for lapping a bar using a patterned probe Feb 28, 2008 Issued
Array ( [id] => 4554480 [patent_doc_number] => 07960982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Supply current based testing of CMOS output stages' [patent_app_type] => utility [patent_app_number] => 12/074081 [patent_app_country] => US [patent_app_date] => 2008-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2299 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/960/07960982.pdf [firstpage_image] =>[orig_patent_app_number] => 12074081 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/074081
Supply current based testing of CMOS output stages Feb 28, 2008 Issued
Array ( [id] => 54435 [patent_doc_number] => 07772867 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'Structures for testing and locating defects in integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/037687 [patent_app_country] => US [patent_app_date] => 2008-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7434 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/772/07772867.pdf [firstpage_image] =>[orig_patent_app_number] => 12037687 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/037687
Structures for testing and locating defects in integrated circuits Feb 25, 2008 Issued
Array ( [id] => 5282799 [patent_doc_number] => 20090096473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-16 [patent_title] => 'TESTING PROBE AND ELECTRICAL CONNECTION METHOD USING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/032699 [patent_app_country] => US [patent_app_date] => 2008-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2778 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20090096473.pdf [firstpage_image] =>[orig_patent_app_number] => 12032699 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/032699
TESTING PROBE AND ELECTRICAL CONNECTION METHOD USING THE SAME Feb 17, 2008 Abandoned
Array ( [id] => 5833 [patent_doc_number] => 07812595 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-12 [patent_title] => 'Electronic device identifying method' [patent_app_type] => utility [patent_app_number] => 12/032998 [patent_app_country] => US [patent_app_date] => 2008-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 12105 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/812/07812595.pdf [firstpage_image] =>[orig_patent_app_number] => 12032998 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/032998
Electronic device identifying method Feb 17, 2008 Issued
Array ( [id] => 5389556 [patent_doc_number] => 20090206868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'METHODOLOGIES AND TOOL SET FOR IDDQ VERIFICATION, DEBUGGING AND FAILURE DIAGNOSIS' [patent_app_type] => utility [patent_app_number] => 12/032492 [patent_app_country] => US [patent_app_date] => 2008-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11281 [patent_no_of_claims] => 75 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20090206868.pdf [firstpage_image] =>[orig_patent_app_number] => 12032492 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/032492
Methodologies and tool set for IDDQ verification, debugging and failure diagnosis Feb 14, 2008 Issued
Array ( [id] => 5478086 [patent_doc_number] => 20090201043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-13 [patent_title] => 'Crack Sensors for Semiconductor Devices' [patent_app_type] => utility [patent_app_number] => 12/030799 [patent_app_country] => US [patent_app_date] => 2008-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7790 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20090201043.pdf [firstpage_image] =>[orig_patent_app_number] => 12030799 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/030799
Crack sensors for semiconductor devices Feb 12, 2008 Issued
Array ( [id] => 4783106 [patent_doc_number] => 20080136435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'CLAMPING TOP PLATE USING MAGNETIC FORCE' [patent_app_type] => utility [patent_app_number] => 12/030475 [patent_app_country] => US [patent_app_date] => 2008-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1595 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20080136435.pdf [firstpage_image] =>[orig_patent_app_number] => 12030475 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/030475
Clamping top plate using magnetic force Feb 12, 2008 Issued
Array ( [id] => 5377758 [patent_doc_number] => 20090189597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => 'INSTRUMENT FOR TESTING AN ELECTRICAL CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/022793 [patent_app_country] => US [patent_app_date] => 2008-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2774 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20090189597.pdf [firstpage_image] =>[orig_patent_app_number] => 12022793 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/022793
INSTRUMENT FOR TESTING AN ELECTRICAL CIRCUIT Jan 29, 2008 Abandoned
Array ( [id] => 4811096 [patent_doc_number] => 20080191727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'PROBE AND PROBE ASSEMBLY' [patent_app_type] => utility [patent_app_number] => 12/017295 [patent_app_country] => US [patent_app_date] => 2008-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3548 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20080191727.pdf [firstpage_image] =>[orig_patent_app_number] => 12017295 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/017295
PROBE AND PROBE ASSEMBLY Jan 20, 2008 Abandoned
Array ( [id] => 6178632 [patent_doc_number] => 20110121851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'PROBE CARD' [patent_app_type] => utility [patent_app_number] => 12/674277 [patent_app_country] => US [patent_app_date] => 2008-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3829 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20110121851.pdf [firstpage_image] =>[orig_patent_app_number] => 12674277 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/674277
Probe card having a plurality of space transformers Jan 7, 2008 Issued
Array ( [id] => 6324326 [patent_doc_number] => 20100244878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'PLL BURN-IN CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/521192 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9884 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20100244878.pdf [firstpage_image] =>[orig_patent_app_number] => 12521192 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/521192
PLL BURN-IN CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT Dec 19, 2007 Abandoned
Array ( [id] => 253190 [patent_doc_number] => 07579826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-25 [patent_title] => 'Test socket for semiconductor' [patent_app_type] => utility [patent_app_number] => 11/960993 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2711 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/579/07579826.pdf [firstpage_image] =>[orig_patent_app_number] => 11960993 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/960993
Test socket for semiconductor Dec 19, 2007 Issued
Array ( [id] => 4635154 [patent_doc_number] => 08013610 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-09-06 [patent_title] => 'High-Q self tuning locating transmitter' [patent_app_type] => utility [patent_app_number] => 11/961858 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 7519 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/013/08013610.pdf [firstpage_image] =>[orig_patent_app_number] => 11961858 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/961858
High-Q self tuning locating transmitter Dec 19, 2007 Issued
Array ( [id] => 43992 [patent_doc_number] => 07782071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Probe card analysis system and method' [patent_app_type] => utility [patent_app_number] => 11/960597 [patent_app_country] => US [patent_app_date] => 2007-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4949 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/782/07782071.pdf [firstpage_image] =>[orig_patent_app_number] => 11960597 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/960597
Probe card analysis system and method Dec 18, 2007 Issued
Array ( [id] => 6241483 [patent_doc_number] => 20100134137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-03 [patent_title] => 'LIQUID CRYSTAL DISPLAY PANEL AND ITS INSPECTING METHOD' [patent_app_type] => utility [patent_app_number] => 12/597444 [patent_app_country] => US [patent_app_date] => 2007-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12226 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20100134137.pdf [firstpage_image] =>[orig_patent_app_number] => 12597444 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/597444
LIQUID CRYSTAL DISPLAY PANEL AND ITS INSPECTING METHOD Dec 12, 2007 Abandoned
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