Search

Ben M. Rifkin

Examiner (ID: 13211, Phone: (571)272-9768 , Office: P/2122 )

Most Active Art Unit
2122
Art Unit(s)
2122, 2129, 2198, 2124, 2123
Total Applications
534
Issued Applications
224
Pending Applications
86
Abandoned Applications
235

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6023861 [patent_doc_number] => 20110052187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'TIME DIVISION MULTIPLEXED DETECTOR FOR A MAGNETO-OPTICAL CURRENT TRANSDUCER' [patent_app_type] => utility [patent_app_number] => 12/517899 [patent_app_country] => US [patent_app_date] => 2007-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2331 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20110052187.pdf [firstpage_image] =>[orig_patent_app_number] => 12517899 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/517899
Time division multiplexed detector for a magneto-optical current transducer Dec 10, 2007 Issued
Array ( [id] => 8357092 [patent_doc_number] => 20120212248 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2012-08-23 [patent_title] => 'Construction Structures and Manufacturing Processes for Integrated Circuit Wafer Probe Card Assemblies' [patent_app_type] => utility [patent_app_number] => 12/517528 [patent_app_country] => US [patent_app_date] => 2007-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 14809 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12517528 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/517528
Construction Structures and Manufacturing Processes for Integrated Circuit Wafer Probe Card Assemblies Dec 3, 2007 Abandoned
Array ( [id] => 8357092 [patent_doc_number] => 20120212248 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2012-08-23 [patent_title] => 'Construction Structures and Manufacturing Processes for Integrated Circuit Wafer Probe Card Assemblies' [patent_app_type] => utility [patent_app_number] => 12/517528 [patent_app_country] => US [patent_app_date] => 2007-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 14809 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12517528 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/517528
Construction Structures and Manufacturing Processes for Integrated Circuit Wafer Probe Card Assemblies Dec 3, 2007 Abandoned
Array ( [id] => 588949 [patent_doc_number] => 07446550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'Enhanced signal observability for circuit analysis' [patent_app_type] => utility [patent_app_number] => 11/949325 [patent_app_country] => US [patent_app_date] => 2007-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5691 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/446/07446550.pdf [firstpage_image] =>[orig_patent_app_number] => 11949325 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/949325
Enhanced signal observability for circuit analysis Dec 2, 2007 Issued
Array ( [id] => 5573359 [patent_doc_number] => 20090140720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'METHOD FOR IDENTIFYING ELECTRONIC CIRCUITS AND IDENTIFICATION DEVICE' [patent_app_type] => utility [patent_app_number] => 11/949398 [patent_app_country] => US [patent_app_date] => 2007-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3835 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20090140720.pdf [firstpage_image] =>[orig_patent_app_number] => 11949398 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/949398
Method for identifying electronic circuits and identification device Dec 2, 2007 Issued
Array ( [id] => 4938926 [patent_doc_number] => 20080076245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY AND A FABRICATION METHOD FOR THE SAME' [patent_app_type] => utility [patent_app_number] => 11/947396 [patent_app_country] => US [patent_app_date] => 2007-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 9207 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20080076245.pdf [firstpage_image] =>[orig_patent_app_number] => 11947396 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/947396
Nonvolatile semiconductor memory and a fabrication method for the same Nov 28, 2007 Issued
Array ( [id] => 4891233 [patent_doc_number] => 20080100330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'TEST APPARATUS, PERFORMANCE BOARD AND INTERFACE PLATE' [patent_app_type] => utility [patent_app_number] => 11/945993 [patent_app_country] => US [patent_app_date] => 2007-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7282 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20080100330.pdf [firstpage_image] =>[orig_patent_app_number] => 11945993 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/945993
TEST APPARATUS, PERFORMANCE BOARD AND INTERFACE PLATE Nov 26, 2007 Abandoned
Array ( [id] => 8665241 [patent_doc_number] => 08378704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-19 [patent_title] => 'Substrate for a probe card assembly' [patent_app_type] => utility [patent_app_number] => 11/943105 [patent_app_country] => US [patent_app_date] => 2007-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 3764 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11943105 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/943105
Substrate for a probe card assembly Nov 19, 2007 Issued
Array ( [id] => 4864310 [patent_doc_number] => 20080143369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'ELECTRICAL CONNECTING APPARATUS AND METHOD FOR USE THEREOF' [patent_app_type] => utility [patent_app_number] => 11/939495 [patent_app_country] => US [patent_app_date] => 2007-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3984 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20080143369.pdf [firstpage_image] =>[orig_patent_app_number] => 11939495 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/939495
Electrical connecting apparatus and method for use thereof Nov 12, 2007 Issued
Array ( [id] => 4902392 [patent_doc_number] => 20080111805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'Liquid crystal display having common voltage initialization circuit and method for manufacturing same' [patent_app_type] => utility [patent_app_number] => 11/985297 [patent_app_country] => US [patent_app_date] => 2007-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2549 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20080111805.pdf [firstpage_image] =>[orig_patent_app_number] => 11985297 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/985297
Liquid crystal display having common voltage initialization circuit and method for manufacturing same Nov 12, 2007 Issued
Array ( [id] => 585047 [patent_doc_number] => 07453274 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-11-18 [patent_title] => 'Detection of defects using transient contrast' [patent_app_type] => utility [patent_app_number] => 11/982096 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4467 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/453/07453274.pdf [firstpage_image] =>[orig_patent_app_number] => 11982096 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/982096
Detection of defects using transient contrast Oct 30, 2007 Issued
Array ( [id] => 6605556 [patent_doc_number] => 20100033199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-11 [patent_title] => 'HOLDING MEMBER FOR INSPECTION, INSPECTION DEVICE AND INSPECTING METHOD' [patent_app_type] => utility [patent_app_number] => 12/444695 [patent_app_country] => US [patent_app_date] => 2007-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4673 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20100033199.pdf [firstpage_image] =>[orig_patent_app_number] => 12444695 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/444695
Holding member for inspection, inspection device and inspecting method Oct 16, 2007 Issued
Array ( [id] => 6248160 [patent_doc_number] => 20100026325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'METHOD AND DEVICE FOR DETECTING STRUCTURAL ABNORMALITIES IN A SPHERICAL PARTICLE, PARTICULARLY IN A NUCLEAR FUEL PARTICLE FOR HIGH TEMPERATURE OR VERY HIGH TEMPERATURE REACTORS' [patent_app_type] => utility [patent_app_number] => 12/445209 [patent_app_country] => US [patent_app_date] => 2007-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3503 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20100026325.pdf [firstpage_image] =>[orig_patent_app_number] => 12445209 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/445209
Method and device for detecting structural abnormalities in a spherical particle Oct 10, 2007 Issued
Array ( [id] => 4691429 [patent_doc_number] => 20080084199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'METHOD FOR ELIMINATING THE NEED TO ZERO AND CALIBRATE A POWER METER BEFORE USE' [patent_app_type] => utility [patent_app_number] => 11/869594 [patent_app_country] => US [patent_app_date] => 2007-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5760 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20080084199.pdf [firstpage_image] =>[orig_patent_app_number] => 11869594 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/869594
Power meter with means to eliminate the need to zero and calibrating Oct 8, 2007 Issued
Array ( [id] => 4963468 [patent_doc_number] => 20080106288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'Circuit boards including removable test point portions and configurable testing platforms' [patent_app_type] => utility [patent_app_number] => 11/973793 [patent_app_country] => US [patent_app_date] => 2007-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6593 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20080106288.pdf [firstpage_image] =>[orig_patent_app_number] => 11973793 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/973793
Circuit boards including removable test point portions and configurable testing platforms Oct 8, 2007 Issued
Array ( [id] => 4695970 [patent_doc_number] => 20080218154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Integrated energy metering system' [patent_app_type] => utility [patent_app_number] => 11/906394 [patent_app_country] => US [patent_app_date] => 2007-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4701 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20080218154.pdf [firstpage_image] =>[orig_patent_app_number] => 11906394 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/906394
Integrated energy metering system Oct 1, 2007 Issued
Array ( [id] => 9778840 [patent_doc_number] => 08854049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Timer unit, system, computer program product and method for testing a logic circuit' [patent_app_type] => utility [patent_app_number] => 12/676699 [patent_app_country] => US [patent_app_date] => 2007-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12676699 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/676699
Timer unit, system, computer program product and method for testing a logic circuit Sep 24, 2007 Issued
Array ( [id] => 4794805 [patent_doc_number] => 20080006391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-10 [patent_title] => 'Apparatus and Method for the Application of Prescribed, Predicted, and Controlled Contact Pressure on Wires' [patent_app_type] => utility [patent_app_number] => 11/859477 [patent_app_country] => US [patent_app_date] => 2007-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10161 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20080006391.pdf [firstpage_image] =>[orig_patent_app_number] => 11859477 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/859477
Apparatus and method for the application of prescribed, predicted, and controlled contact pressure on wires Sep 20, 2007 Issued
Array ( [id] => 4795701 [patent_doc_number] => 20080007287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-10 [patent_title] => 'PANEL AND TEST METHOD FOR DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/857889 [patent_app_country] => US [patent_app_date] => 2007-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4025 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20080007287.pdf [firstpage_image] =>[orig_patent_app_number] => 11857889 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/857889
Panel and test method for display device Sep 18, 2007 Issued
Array ( [id] => 5562073 [patent_doc_number] => 20090134925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-28 [patent_title] => 'APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES' [patent_app_type] => utility [patent_app_number] => 11/857596 [patent_app_country] => US [patent_app_date] => 2007-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5169 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20090134925.pdf [firstpage_image] =>[orig_patent_app_number] => 11857596 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/857596
Apparatus and method for hardening latches in SOI CMOS devices Sep 18, 2007 Issued
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