Search

Benjamin A. Schiffman

Examiner (ID: 16931, Phone: (571)270-7626 , Office: P/1742 )

Most Active Art Unit
1742
Art Unit(s)
1791, 1742, 4191
Total Applications
1223
Issued Applications
800
Pending Applications
72
Abandoned Applications
367

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 393943 [patent_doc_number] => 07297636 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-11-20 [patent_title] => 'Methods for fabricating device features having small dimensions' [patent_app_type] => utility [patent_app_number] => 11/669389 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2270 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/297/07297636.pdf [firstpage_image] =>[orig_patent_app_number] => 11669389 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/669389
Methods for fabricating device features having small dimensions Jan 30, 2007 Issued
Array ( [id] => 888063 [patent_doc_number] => 07348270 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-03-25 [patent_title] => 'Techniques for forming interconnects' [patent_app_type] => utility [patent_app_number] => 11/625449 [patent_app_country] => US [patent_app_date] => 2007-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3900 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/348/07348270.pdf [firstpage_image] =>[orig_patent_app_number] => 11625449 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/625449
Techniques for forming interconnects Jan 21, 2007 Issued
Array ( [id] => 4971493 [patent_doc_number] => 20070111495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Contact hole structure of semiconductor device and method of forming the same' [patent_app_type] => utility [patent_app_number] => 11/598709 [patent_app_country] => US [patent_app_date] => 2006-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2313 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20070111495.pdf [firstpage_image] =>[orig_patent_app_number] => 11598709 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/598709
Contact hole structure of semiconductor device and method of forming the same Nov 13, 2006 Issued
Array ( [id] => 443713 [patent_doc_number] => 07256473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-14 [patent_title] => 'Composite structure with high heat dissipation' [patent_app_type] => utility [patent_app_number] => 11/539310 [patent_app_country] => US [patent_app_date] => 2006-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 7071 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/256/07256473.pdf [firstpage_image] =>[orig_patent_app_number] => 11539310 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/539310
Composite structure with high heat dissipation Oct 5, 2006 Issued
Array ( [id] => 860319 [patent_doc_number] => 07371664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-13 [patent_title] => 'Process for wafer thinning' [patent_app_type] => utility [patent_app_number] => 11/527489 [patent_app_country] => US [patent_app_date] => 2006-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1105 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/371/07371664.pdf [firstpage_image] =>[orig_patent_app_number] => 11527489 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/527489
Process for wafer thinning Sep 26, 2006 Issued
Array ( [id] => 5138993 [patent_doc_number] => 20070001209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'Method of forming a storage electrode of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/516707 [patent_app_country] => US [patent_app_date] => 2006-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7317 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20070001209.pdf [firstpage_image] =>[orig_patent_app_number] => 11516707 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/516707
Method of forming a storage electrode of a semiconductor device Sep 6, 2006 Issued
Array ( [id] => 5183149 [patent_doc_number] => 20070054503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-08 [patent_title] => 'Film forming method and fabrication process of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/510679 [patent_app_country] => US [patent_app_date] => 2006-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5753 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20070054503.pdf [firstpage_image] =>[orig_patent_app_number] => 11510679 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/510679
Film forming method and fabrication process of semiconductor device Aug 27, 2006 Abandoned
Array ( [id] => 5622891 [patent_doc_number] => 20060261396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Multiple stacked capacitors formed within an opening with thick capacitor dielectric' [patent_app_type] => utility [patent_app_number] => 11/496384 [patent_app_country] => US [patent_app_date] => 2006-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8987 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20060261396.pdf [firstpage_image] =>[orig_patent_app_number] => 11496384 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/496384
Multiple stacked capacitors formed within an opening with thick capacitor dielectric Jul 30, 2006 Issued
Array ( [id] => 4983011 [patent_doc_number] => 20070087569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/479288 [patent_app_country] => US [patent_app_date] => 2006-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1543 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20070087569.pdf [firstpage_image] =>[orig_patent_app_number] => 11479288 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/479288
Method for fabricating semiconductor device Jun 28, 2006 Abandoned
Array ( [id] => 892023 [patent_doc_number] => 07344987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-18 [patent_title] => 'Method for CMP with variable down-force adjustment' [patent_app_type] => utility [patent_app_number] => 11/445669 [patent_app_country] => US [patent_app_date] => 2006-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 4019 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/344/07344987.pdf [firstpage_image] =>[orig_patent_app_number] => 11445669 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/445669
Method for CMP with variable down-force adjustment Jun 1, 2006 Issued
Array ( [id] => 404634 [patent_doc_number] => 07288463 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-30 [patent_title] => 'Pulsed deposition layer gap fill with expansion material' [patent_app_type] => utility [patent_app_number] => 11/414459 [patent_app_country] => US [patent_app_date] => 2006-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5985 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/288/07288463.pdf [firstpage_image] =>[orig_patent_app_number] => 11414459 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/414459
Pulsed deposition layer gap fill with expansion material Apr 27, 2006 Issued
Array ( [id] => 4994757 [patent_doc_number] => 20070010102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A STRUCTURE OF A SINGLE CRYSTAL SCANDIUM OXIDE FILM FORMED ON A SILICON SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 11/380518 [patent_app_country] => US [patent_app_date] => 2006-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3291 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20070010102.pdf [firstpage_image] =>[orig_patent_app_number] => 11380518 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/380518
Method for forming a semiconductor device having a structure of a single crystal scandium oxide film formed on a silicon substrate Apr 26, 2006 Issued
Array ( [id] => 5703192 [patent_doc_number] => 20060192239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'Permeable capacitor electrode' [patent_app_type] => utility [patent_app_number] => 11/414661 [patent_app_country] => US [patent_app_date] => 2006-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9752 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20060192239.pdf [firstpage_image] =>[orig_patent_app_number] => 11414661 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/414661
Permeable capacitor electrode Apr 26, 2006 Issued
Array ( [id] => 5785581 [patent_doc_number] => 20060205142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'Methods of forming semiconductor constructions' [patent_app_type] => utility [patent_app_number] => 11/375696 [patent_app_country] => US [patent_app_date] => 2006-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3480 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20060205142.pdf [firstpage_image] =>[orig_patent_app_number] => 11375696 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/375696
Methods of forming semiconductor constructions Mar 12, 2006 Issued
Array ( [id] => 928527 [patent_doc_number] => 07314837 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-01 [patent_title] => 'Chemical treatment of semiconductor substrates' [patent_app_type] => utility [patent_app_number] => 11/333629 [patent_app_country] => US [patent_app_date] => 2005-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5636 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/314/07314837.pdf [firstpage_image] =>[orig_patent_app_number] => 11333629 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/333629
Chemical treatment of semiconductor substrates Dec 28, 2005 Issued
Array ( [id] => 813700 [patent_doc_number] => 07413972 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-19 [patent_title] => 'Method of forming a metal interconnection line in a semiconductor device using an FSG layer' [patent_app_type] => utility [patent_app_number] => 11/313698 [patent_app_country] => US [patent_app_date] => 2005-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 1966 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/413/07413972.pdf [firstpage_image] =>[orig_patent_app_number] => 11313698 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/313698
Method of forming a metal interconnection line in a semiconductor device using an FSG layer Dec 21, 2005 Issued
Array ( [id] => 5649192 [patent_doc_number] => 20060134927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Method for forming ultra thin oxide layer by ozonated water' [patent_app_type] => utility [patent_app_number] => 11/303938 [patent_app_country] => US [patent_app_date] => 2005-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1565 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20060134927.pdf [firstpage_image] =>[orig_patent_app_number] => 11303938 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/303938
Method for forming ultra thin oxide layer by ozonated water Dec 18, 2005 Abandoned
Array ( [id] => 435864 [patent_doc_number] => 07262120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-28 [patent_title] => 'Method for fabricating metal line in semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/298758 [patent_app_country] => US [patent_app_date] => 2005-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1893 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/262/07262120.pdf [firstpage_image] =>[orig_patent_app_number] => 11298758 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/298758
Method for fabricating metal line in semiconductor device Dec 8, 2005 Issued
Array ( [id] => 5851316 [patent_doc_number] => 20060234507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-19 [patent_title] => 'Treatment of semiconductor wafers' [patent_app_type] => utility [patent_app_number] => 11/256348 [patent_app_country] => US [patent_app_date] => 2005-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3147 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20060234507.pdf [firstpage_image] =>[orig_patent_app_number] => 11256348 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/256348
Treatment of semiconductor wafers Oct 19, 2005 Issued
Array ( [id] => 397612 [patent_doc_number] => 07294581 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-13 [patent_title] => 'Method for fabricating silicon nitride spacer structures' [patent_app_type] => utility [patent_app_number] => 11/253229 [patent_app_country] => US [patent_app_date] => 2005-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4293 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/294/07294581.pdf [firstpage_image] =>[orig_patent_app_number] => 11253229 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/253229
Method for fabricating silicon nitride spacer structures Oct 16, 2005 Issued
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