
Benjamin A. Schiffman
Examiner (ID: 12059)
| Most Active Art Unit | 1742 |
| Art Unit(s) | 1742, 1791, 4191 |
| Total Applications | 1236 |
| Issued Applications | 807 |
| Pending Applications | 77 |
| Abandoned Applications | 367 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4344208
[patent_doc_number] => 06284616
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-04
[patent_title] => 'Circuit and method for reducing parasitic bipolar effects during electrostatic discharges'
[patent_app_type] => 1
[patent_app_number] => 9/560501
[patent_app_country] => US
[patent_app_date] => 2000-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 4924
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/284/06284616.pdf
[firstpage_image] =>[orig_patent_app_number] => 560501
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/560501 | Circuit and method for reducing parasitic bipolar effects during electrostatic discharges | Apr 26, 2000 | Issued |
Array
(
[id] => 1477934
[patent_doc_number] => 06451622
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-17
[patent_title] => 'Optical device'
[patent_app_type] => B1
[patent_app_number] => 09/558331
[patent_app_country] => US
[patent_app_date] => 2000-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 32
[patent_no_of_words] => 11031
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/451/06451622.pdf
[firstpage_image] =>[orig_patent_app_number] => 09558331
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/558331 | Optical device | Apr 25, 2000 | Issued |
Array
(
[id] => 1273999
[patent_doc_number] => 06649508
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-11-18
[patent_title] => 'Methods of forming self-aligned contact structures in semiconductor integrated circuit devices'
[patent_app_type] => B1
[patent_app_number] => 09/556499
[patent_app_country] => US
[patent_app_date] => 2000-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 4556
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/649/06649508.pdf
[firstpage_image] =>[orig_patent_app_number] => 09556499
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/556499 | Methods of forming self-aligned contact structures in semiconductor integrated circuit devices | Apr 23, 2000 | Issued |
Array
(
[id] => 4377146
[patent_doc_number] => 06303412
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-16
[patent_title] => 'Methods of forming semiconductor-on-insulator substrates and devices and structures formed thereby'
[patent_app_type] => 1
[patent_app_number] => 9/541201
[patent_app_country] => US
[patent_app_date] => 2000-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 2006
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/303/06303412.pdf
[firstpage_image] =>[orig_patent_app_number] => 541201
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/541201 | Methods of forming semiconductor-on-insulator substrates and devices and structures formed thereby | Apr 2, 2000 | Issued |
Array
(
[id] => 4259706
[patent_doc_number] => 06258724
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-10
[patent_title] => 'Low dielectric constant dielectric films and process for making the same'
[patent_app_type] => 1
[patent_app_number] => 9/541160
[patent_app_country] => US
[patent_app_date] => 2000-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 6835
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/258/06258724.pdf
[firstpage_image] =>[orig_patent_app_number] => 541160
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/541160 | Low dielectric constant dielectric films and process for making the same | Mar 30, 2000 | Issued |
Array
(
[id] => 1565690
[patent_doc_number] => 06376293
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-23
[patent_title] => 'Shallow drain extenders for CMOS transistors using replacement gate design'
[patent_app_type] => B1
[patent_app_number] => 09/537271
[patent_app_country] => US
[patent_app_date] => 2000-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 15
[patent_no_of_words] => 3002
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/376/06376293.pdf
[firstpage_image] =>[orig_patent_app_number] => 09537271
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/537271 | Shallow drain extenders for CMOS transistors using replacement gate design | Mar 28, 2000 | Issued |
Array
(
[id] => 1509190
[patent_doc_number] => 06467075
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-15
[patent_title] => 'Resolution of dynamic memory allocation/deallocation and pointers'
[patent_app_type] => B1
[patent_app_number] => 09/533808
[patent_app_country] => US
[patent_app_date] => 2000-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 9907
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/467/06467075.pdf
[firstpage_image] =>[orig_patent_app_number] => 09533808
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/533808 | Resolution of dynamic memory allocation/deallocation and pointers | Mar 23, 2000 | Issued |
Array
(
[id] => 1460277
[patent_doc_number] => 06463576
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-08
[patent_title] => 'Method for designing an ASIC and ASIC designing apparatus'
[patent_app_type] => B1
[patent_app_number] => 09/531717
[patent_app_country] => US
[patent_app_date] => 2000-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3916
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/463/06463576.pdf
[firstpage_image] =>[orig_patent_app_number] => 09531717
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/531717 | Method for designing an ASIC and ASIC designing apparatus | Mar 20, 2000 | Issued |
Array
(
[id] => 1366625
[patent_doc_number] => 06566173
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-20
[patent_title] => 'Polycrystalline silicon thin film transistor and manufacturing method thereof'
[patent_app_type] => B1
[patent_app_number] => 09/528030
[patent_app_country] => US
[patent_app_date] => 2000-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2191
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/566/06566173.pdf
[firstpage_image] =>[orig_patent_app_number] => 09528030
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/528030 | Polycrystalline silicon thin film transistor and manufacturing method thereof | Mar 16, 2000 | Issued |
Array
(
[id] => 1523630
[patent_doc_number] => 06352884
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-05
[patent_title] => 'Method for growing crystals having impurities and crystals prepared thereby'
[patent_app_type] => B1
[patent_app_number] => 09/528250
[patent_app_country] => US
[patent_app_date] => 2000-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 22
[patent_no_of_words] => 3366
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/352/06352884.pdf
[firstpage_image] =>[orig_patent_app_number] => 09528250
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/528250 | Method for growing crystals having impurities and crystals prepared thereby | Mar 16, 2000 | Issued |
Array
(
[id] => 1459226
[patent_doc_number] => 06391677
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-21
[patent_title] => 'Aperture for an exposure apparatus for forming a fine pattern on a semiconductor wafer'
[patent_app_type] => B1
[patent_app_number] => 09/527391
[patent_app_country] => US
[patent_app_date] => 2000-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7669
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 28
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/391/06391677.pdf
[firstpage_image] =>[orig_patent_app_number] => 09527391
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/527391 | Aperture for an exposure apparatus for forming a fine pattern on a semiconductor wafer | Mar 15, 2000 | Issued |
Array
(
[id] => 7645823
[patent_doc_number] => 06477700
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-05
[patent_title] => 'Reticle having discriminative pattern narrower in pitch than the minimum pattern width but wider than minimum width in the pattern recognition'
[patent_app_type] => B1
[patent_app_number] => 09/526525
[patent_app_country] => US
[patent_app_date] => 2000-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2145
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 14
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/477/06477700.pdf
[firstpage_image] =>[orig_patent_app_number] => 09526525
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/526525 | Reticle having discriminative pattern narrower in pitch than the minimum pattern width but wider than minimum width in the pattern recognition | Mar 15, 2000 | Issued |
Array
(
[id] => 4259168
[patent_doc_number] => 06258688
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-10
[patent_title] => 'Method to form a high Q inductor'
[patent_app_type] => 1
[patent_app_number] => 9/525671
[patent_app_country] => US
[patent_app_date] => 2000-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 4300
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 296
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/258/06258688.pdf
[firstpage_image] =>[orig_patent_app_number] => 525671
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/525671 | Method to form a high Q inductor | Mar 14, 2000 | Issued |
Array
(
[id] => 1425912
[patent_doc_number] => 06536029
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-18
[patent_title] => 'Programmable logic controller method, system and apparatus'
[patent_app_type] => B1
[patent_app_number] => 09/526115
[patent_app_country] => US
[patent_app_date] => 2000-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
[patent_figures_cnt] => 57
[patent_no_of_words] => 15850
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/536/06536029.pdf
[firstpage_image] =>[orig_patent_app_number] => 09526115
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/526115 | Programmable logic controller method, system and apparatus | Mar 14, 2000 | Issued |
Array
(
[id] => 7644090
[patent_doc_number] => 06473884
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-29
[patent_title] => 'Method and system for equivalence-checking combinatorial circuits using interative binary-decision-diagram sweeping and structural satisfiability analysis'
[patent_app_type] => B1
[patent_app_number] => 09/524890
[patent_app_country] => US
[patent_app_date] => 2000-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 2594
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 4
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/473/06473884.pdf
[firstpage_image] =>[orig_patent_app_number] => 09524890
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/524890 | Method and system for equivalence-checking combinatorial circuits using interative binary-decision-diagram sweeping and structural satisfiability analysis | Mar 13, 2000 | Issued |
Array
(
[id] => 4381537
[patent_doc_number] => 06294451
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-25
[patent_title] => 'Semiconductor device and method for manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 9/524690
[patent_app_country] => US
[patent_app_date] => 2000-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 3696
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/294/06294451.pdf
[firstpage_image] =>[orig_patent_app_number] => 524690
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/524690 | Semiconductor device and method for manufacturing the same | Mar 13, 2000 | Issued |
Array
(
[id] => 1523569
[patent_doc_number] => 06352868
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-05
[patent_title] => 'Method and apparatus for wafer level burn-in'
[patent_app_type] => B1
[patent_app_number] => 09/524421
[patent_app_country] => US
[patent_app_date] => 2000-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 3711
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/352/06352868.pdf
[firstpage_image] =>[orig_patent_app_number] => 09524421
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/524421 | Method and apparatus for wafer level burn-in | Mar 10, 2000 | Issued |
Array
(
[id] => 1361859
[patent_doc_number] => 06569752
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-27
[patent_title] => 'Semiconductor element and fabricating method thereof'
[patent_app_type] => B1
[patent_app_number] => 09/522820
[patent_app_country] => US
[patent_app_date] => 2000-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 24
[patent_no_of_words] => 7219
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/569/06569752.pdf
[firstpage_image] =>[orig_patent_app_number] => 09522820
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/522820 | Semiconductor element and fabricating method thereof | Mar 9, 2000 | Issued |
Array
(
[id] => 1339805
[patent_doc_number] => 06589839
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-08
[patent_title] => 'Dielectric cure for reducing oxygen vacancies'
[patent_app_type] => B1
[patent_app_number] => 09/522627
[patent_app_country] => US
[patent_app_date] => 2000-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 7848
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/589/06589839.pdf
[firstpage_image] =>[orig_patent_app_number] => 09522627
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/522627 | Dielectric cure for reducing oxygen vacancies | Mar 9, 2000 | Issued |
Array
(
[id] => 1477583
[patent_doc_number] => 06344372
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-05
[patent_title] => 'Semiconductor device with reliable connection between projective electrode and conductive wire of the substrate'
[patent_app_type] => B1
[patent_app_number] => 09/521890
[patent_app_country] => US
[patent_app_date] => 2000-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 18
[patent_no_of_words] => 5179
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/344/06344372.pdf
[firstpage_image] =>[orig_patent_app_number] => 09521890
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/521890 | Semiconductor device with reliable connection between projective electrode and conductive wire of the substrate | Mar 8, 2000 | Issued |