Search

Benjamin A. Schiffman

Examiner (ID: 12059)

Most Active Art Unit
1742
Art Unit(s)
1742, 1791, 4191
Total Applications
1236
Issued Applications
807
Pending Applications
77
Abandoned Applications
367

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1477692 [patent_doc_number] => 06344401 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Method of forming a stacked-die integrated circuit chip package on a water level' [patent_app_type] => B1 [patent_app_number] => 09/521299 [patent_app_country] => US [patent_app_date] => 2000-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2515 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/344/06344401.pdf [firstpage_image] =>[orig_patent_app_number] => 09521299 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/521299
Method of forming a stacked-die integrated circuit chip package on a water level Mar 8, 2000 Issued
Array ( [id] => 1340216 [patent_doc_number] => 06601229 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Client/server behavioral modeling and testcase development using VHDL for improved logic verification' [patent_app_type] => B1 [patent_app_number] => 09/521990 [patent_app_country] => US [patent_app_date] => 2000-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1245 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/601/06601229.pdf [firstpage_image] =>[orig_patent_app_number] => 09521990 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/521990
Client/server behavioral modeling and testcase development using VHDL for improved logic verification Mar 8, 2000 Issued
Array ( [id] => 1449881 [patent_doc_number] => 06455348 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Lead frame, resin-molded semiconductor device, and method for manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/521670 [patent_app_country] => US [patent_app_date] => 2000-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 12899 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/455/06455348.pdf [firstpage_image] =>[orig_patent_app_number] => 09521670 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/521670
Lead frame, resin-molded semiconductor device, and method for manufacturing the same Mar 7, 2000 Issued
Array ( [id] => 4310023 [patent_doc_number] => 06316301 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Method for sizing PMOS pull-up devices' [patent_app_type] => 1 [patent_app_number] => 9/520921 [patent_app_country] => US [patent_app_date] => 2000-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3582 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316301.pdf [firstpage_image] =>[orig_patent_app_number] => 520921 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/520921
Method for sizing PMOS pull-up devices Mar 7, 2000 Issued
Array ( [id] => 4270527 [patent_doc_number] => 06323051 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Method of manufacturing liquid crystal display' [patent_app_type] => 1 [patent_app_number] => 9/520341 [patent_app_country] => US [patent_app_date] => 2000-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 7665 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323051.pdf [firstpage_image] =>[orig_patent_app_number] => 520341 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/520341
Method of manufacturing liquid crystal display Mar 6, 2000 Issued
Array ( [id] => 4271757 [patent_doc_number] => 06323134 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Plasma processing methods and apparatus' [patent_app_type] => 1 [patent_app_number] => 9/519281 [patent_app_country] => US [patent_app_date] => 2000-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5311 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323134.pdf [firstpage_image] =>[orig_patent_app_number] => 519281 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/519281
Plasma processing methods and apparatus Mar 6, 2000 Issued
Array ( [id] => 4408423 [patent_doc_number] => 06309954 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Methods of forming flip chip bumps and related flip chip bump constructions' [patent_app_type] => 1 [patent_app_number] => 9/515271 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 2033 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/309/06309954.pdf [firstpage_image] =>[orig_patent_app_number] => 515271 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/515271
Methods of forming flip chip bumps and related flip chip bump constructions Feb 28, 2000 Issued
Array ( [id] => 1523574 [patent_doc_number] => 06352869 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Active pixel image sensor with shared amplifier read-out' [patent_app_type] => B1 [patent_app_number] => 09/515830 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2484 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/352/06352869.pdf [firstpage_image] =>[orig_patent_app_number] => 09515830 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/515830
Active pixel image sensor with shared amplifier read-out Feb 28, 2000 Issued
Array ( [id] => 4303290 [patent_doc_number] => 06326233 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Semiconductor device, method of fabricating the same and electronic apparatus' [patent_app_type] => 1 [patent_app_number] => 9/511081 [patent_app_country] => US [patent_app_date] => 2000-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 3415 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326233.pdf [firstpage_image] =>[orig_patent_app_number] => 511081 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/511081
Semiconductor device, method of fabricating the same and electronic apparatus Feb 22, 2000 Issued
Array ( [id] => 1514422 [patent_doc_number] => 06420197 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => B1 [patent_app_number] => 09/511371 [patent_app_country] => US [patent_app_date] => 2000-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 14045 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/420/06420197.pdf [firstpage_image] =>[orig_patent_app_number] => 09511371 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/511371
Semiconductor device and method of fabricating the same Feb 22, 2000 Issued
Array ( [id] => 1095875 [patent_doc_number] => 06821822 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-23 [patent_title] => 'Method of manufacturing semiconductor device, molding device for semiconductor device, and semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/424500 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4024 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/821/06821822.pdf [firstpage_image] =>[orig_patent_app_number] => 09424500 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/424500
Method of manufacturing semiconductor device, molding device for semiconductor device, and semiconductor device Feb 21, 2000 Issued
Array ( [id] => 4130791 [patent_doc_number] => 06146933 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Field shield isolated transistor' [patent_app_type] => 1 [patent_app_number] => 9/502460 [patent_app_country] => US [patent_app_date] => 2000-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 5773 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/146/06146933.pdf [firstpage_image] =>[orig_patent_app_number] => 502460 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/502460
Field shield isolated transistor Feb 10, 2000 Issued
Array ( [id] => 1312024 [patent_doc_number] => 06625797 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Means and method for compiling high level software languages into algorithmically equivalent hardware representations' [patent_app_type] => B1 [patent_app_number] => 09/501319 [patent_app_country] => US [patent_app_date] => 2000-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 11771 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625797.pdf [firstpage_image] =>[orig_patent_app_number] => 09501319 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/501319
Means and method for compiling high level software languages into algorithmically equivalent hardware representations Feb 9, 2000 Issued
Array ( [id] => 1485074 [patent_doc_number] => 06365427 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Semiconductor laser device and method for fabrication thereof' [patent_app_type] => B1 [patent_app_number] => 09/501561 [patent_app_country] => US [patent_app_date] => 2000-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4676 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365427.pdf [firstpage_image] =>[orig_patent_app_number] => 09501561 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/501561
Semiconductor laser device and method for fabrication thereof Feb 8, 2000 Issued
Array ( [id] => 1457010 [patent_doc_number] => 06457167 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Gated clock design supporting method, gated clock design supporting apparatus, and computer readable memory storing gated clock design supporting program' [patent_app_type] => B1 [patent_app_number] => 09/500453 [patent_app_country] => US [patent_app_date] => 2000-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 4342 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457167.pdf [firstpage_image] =>[orig_patent_app_number] => 09500453 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/500453
Gated clock design supporting method, gated clock design supporting apparatus, and computer readable memory storing gated clock design supporting program Feb 8, 2000 Issued
Array ( [id] => 6016388 [patent_doc_number] => 20020102789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD IN WHICH CONTACT HOLE IS FILLED WITH SILICON HAVING LOW IMPURITY CONCENTRATION' [patent_app_type] => new [patent_app_number] => 09/497861 [patent_app_country] => US [patent_app_date] => 2000-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6069 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20020102789.pdf [firstpage_image] =>[orig_patent_app_number] => 09497861 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/497861
Semiconductor device and method in which contact hole is filled with silicon having low impurity concentration Feb 3, 2000 Issued
Array ( [id] => 1324460 [patent_doc_number] => 06602793 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Pre-clean chamber' [patent_app_type] => B1 [patent_app_number] => 09/497360 [patent_app_country] => US [patent_app_date] => 2000-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 3504 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/602/06602793.pdf [firstpage_image] =>[orig_patent_app_number] => 09497360 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/497360
Pre-clean chamber Feb 2, 2000 Issued
Array ( [id] => 1180957 [patent_doc_number] => 06737328 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-18 [patent_title] => 'Methods of forming silicon dioxide layers, and methods of forming trench isolation regions' [patent_app_type] => B1 [patent_app_number] => 09/497080 [patent_app_country] => US [patent_app_date] => 2000-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2331 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/737/06737328.pdf [firstpage_image] =>[orig_patent_app_number] => 09497080 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/497080
Methods of forming silicon dioxide layers, and methods of forming trench isolation regions Feb 1, 2000 Issued
Array ( [id] => 4378315 [patent_doc_number] => 06303486 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Method of fabricating copper-based semiconductor devices using a sacrificial dielectric layer and an unconstrained copper anneal' [patent_app_type] => 1 [patent_app_number] => 9/493320 [patent_app_country] => US [patent_app_date] => 2000-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6582 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303486.pdf [firstpage_image] =>[orig_patent_app_number] => 493320 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/493320
Method of fabricating copper-based semiconductor devices using a sacrificial dielectric layer and an unconstrained copper anneal Jan 27, 2000 Issued
Array ( [id] => 1457006 [patent_doc_number] => 06457166 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Constraint generating device for logic synthesis and its constraint generating method' [patent_app_type] => B1 [patent_app_number] => 09/492165 [patent_app_country] => US [patent_app_date] => 2000-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5746 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457166.pdf [firstpage_image] =>[orig_patent_app_number] => 09492165 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/492165
Constraint generating device for logic synthesis and its constraint generating method Jan 26, 2000 Issued
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