
Benjamin A. Schiffman
Examiner (ID: 12059)
| Most Active Art Unit | 1742 |
| Art Unit(s) | 1742, 1791, 4191 |
| Total Applications | 1236 |
| Issued Applications | 807 |
| Pending Applications | 77 |
| Abandoned Applications | 367 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1409882
[patent_doc_number] => 06528407
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-04
[patent_title] => 'Process for producing electrical-connections on a semiconductor package, and semiconductor package'
[patent_app_type] => B1
[patent_app_number] => 09/684410
[patent_app_country] => US
[patent_app_date] => 2000-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 1675
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[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/528/06528407.pdf
[firstpage_image] =>[orig_patent_app_number] => 09684410
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/684410 | Process for producing electrical-connections on a semiconductor package, and semiconductor package | Oct 5, 2000 | Issued |
Array
(
[id] => 1414754
[patent_doc_number] => 06521529
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-18
[patent_title] => 'HDP treatment for reduced nickel silicide bridging'
[patent_app_type] => B1
[patent_app_number] => 09/679880
[patent_app_country] => US
[patent_app_date] => 2000-10-05
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/521/06521529.pdf
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Array
(
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[patent_doc_number] => 06559051
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[patent_kind] => B1
[patent_issue_date] => 2003-05-06
[patent_title] => 'Electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors'
[patent_app_type] => B1
[patent_app_number] => 09/679881
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[patent_app_date] => 2000-10-05
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/679881 | Electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors | Oct 4, 2000 | Issued |
Array
(
[id] => 7643915
[patent_doc_number] => 06429123
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-06
[patent_title] => 'Method of manufacturing buried metal lines having ultra fine features'
[patent_app_type] => B1
[patent_app_number] => 09/679270
[patent_app_country] => US
[patent_app_date] => 2000-10-04
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/679270 | Method of manufacturing buried metal lines having ultra fine features | Oct 3, 2000 | Issued |
Array
(
[id] => 1299854
[patent_doc_number] => 06624076
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[patent_kind] => B1
[patent_issue_date] => 2003-09-23
[patent_title] => 'Semiconductor device and method for fabricating the same'
[patent_app_type] => B1
[patent_app_number] => 09/672860
[patent_app_country] => US
[patent_app_date] => 2000-09-29
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Array
(
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[patent_doc_number] => 06534388
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[patent_kind] => B1
[patent_issue_date] => 2003-03-18
[patent_title] => 'Method to reduce variation in LDD series resistance'
[patent_app_type] => B1
[patent_app_number] => 09/670330
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/670330 | Method to reduce variation in LDD series resistance | Sep 26, 2000 | Issued |
Array
(
[id] => 1163321
[patent_doc_number] => 06759314
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[patent_issue_date] => 2004-07-06
[patent_title] => 'Method for manufacturing semiconductor devices using thermal nitride films as gate insulating films'
[patent_app_type] => B1
[patent_app_number] => 09/670520
[patent_app_country] => US
[patent_app_date] => 2000-09-26
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/670520 | Method for manufacturing semiconductor devices using thermal nitride films as gate insulating films | Sep 25, 2000 | Issued |
Array
(
[id] => 1435870
[patent_doc_number] => 06355513
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[patent_kind] => B1
[patent_issue_date] => 2002-03-12
[patent_title] => 'Asymmetric depletion region for normally off JFET'
[patent_app_type] => B1
[patent_app_number] => 09/669480
[patent_app_country] => US
[patent_app_date] => 2000-09-25
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/669480 | Asymmetric depletion region for normally off JFET | Sep 24, 2000 | Issued |
Array
(
[id] => 1402372
[patent_doc_number] => 06534406
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-18
[patent_title] => 'Method for increasing inductance of on-chip inductors and related structure'
[patent_app_type] => B1
[patent_app_number] => 09/668790
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[patent_app_date] => 2000-09-22
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[firstpage_image] =>[orig_patent_app_number] => 09668790
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/668790 | Method for increasing inductance of on-chip inductors and related structure | Sep 21, 2000 | Issued |
Array
(
[id] => 1264586
[patent_doc_number] => 06660646
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[patent_issue_date] => 2003-12-09
[patent_title] => 'Method for plasma hardening photoresist in etching of semiconductor and superconductor films'
[patent_app_type] => B1
[patent_app_number] => 09/668250
[patent_app_country] => US
[patent_app_date] => 2000-09-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/668250 | Method for plasma hardening photoresist in etching of semiconductor and superconductor films | Sep 20, 2000 | Issued |
Array
(
[id] => 1553385
[patent_doc_number] => 06348356
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[patent_issue_date] => 2002-02-19
[patent_title] => 'Method and apparatus for determining the robustness of memory cells to alpha-particle/cosmic ray induced soft errors'
[patent_app_type] => B1
[patent_app_number] => 09/664636
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/664636 | Method and apparatus for determining the robustness of memory cells to alpha-particle/cosmic ray induced soft errors | Sep 18, 2000 | Issued |
Array
(
[id] => 4322217
[patent_doc_number] => 06331493
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[patent_title] => 'Process for making low dielectric constant dielectric films'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/653299 | Process for making low dielectric constant dielectric films | Aug 30, 2000 | Issued |
Array
(
[id] => 1235714
[patent_doc_number] => 06689668
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[patent_issue_date] => 2004-02-10
[patent_title] => 'Methods to improve density and uniformity of hemispherical grain silicon layers'
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Array
(
[id] => 1390981
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[patent_title] => 'Energy beam patterning of protective layers for semiconductor devices'
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Array
(
[id] => 1588890
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[patent_title] => 'Integrated circuit asymmetric transistors'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/652900 | Integrated circuit asymmetric transistors | Aug 30, 2000 | Issued |
Array
(
[id] => 1399092
[patent_doc_number] => 06537891
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[patent_title] => 'Silicon on insulator DRAM process utilizing both fully and partially depleted devices'
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Array
(
[id] => 1071893
[patent_doc_number] => 06841477
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[patent_issue_date] => 2005-01-11
[patent_title] => 'Metal interconnection, semiconductor device, method for forming metal interconnection and method for fabricating semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/648750 | Metal interconnection, semiconductor device, method for forming metal interconnection and method for fabricating semiconductor device | Aug 27, 2000 | Issued |
Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/644941 | Method of forming a MIS capacitor | Aug 22, 2000 | Issued |
Array
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[patent_title] => 'Semiconductor memory device capable of correctly and surely effecting voltage stress acceleration'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/642751 | Semiconductor memory device capable of correctly and surely effecting voltage stress acceleration | Aug 17, 2000 | Issued |