Search

Benjamin Driscoll

Examiner (ID: 14622)

Most Active Art Unit
2509
Art Unit(s)
2878, 2509
Total Applications
368
Issued Applications
304
Pending Applications
18
Abandoned Applications
46

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3693718 [patent_doc_number] => 05691655 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Bus driver circuit configured to partially discharge a bus conductor to decrease line to line coupling capacitance' [patent_app_type] => 1 [patent_app_number] => 8/562682 [patent_app_country] => US [patent_app_date] => 1995-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5652 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/691/05691655.pdf [firstpage_image] =>[orig_patent_app_number] => 562682 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/562682
Bus driver circuit configured to partially discharge a bus conductor to decrease line to line coupling capacitance Nov 26, 1995 Issued
Array ( [id] => 3734409 [patent_doc_number] => 05703501 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'Apparatus and method for precharging a bus to an intermediate level' [patent_app_type] => 1 [patent_app_number] => 8/563782 [patent_app_country] => US [patent_app_date] => 1995-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 4114 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/703/05703501.pdf [firstpage_image] =>[orig_patent_app_number] => 563782 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/563782
Apparatus and method for precharging a bus to an intermediate level Nov 26, 1995 Issued
Array ( [id] => 3693235 [patent_doc_number] => 05696453 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'GaAs logic circuit with temperature compensation circuitry' [patent_app_type] => 1 [patent_app_number] => 8/560570 [patent_app_country] => US [patent_app_date] => 1995-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4140 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696453.pdf [firstpage_image] =>[orig_patent_app_number] => 560570 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/560570
GaAs logic circuit with temperature compensation circuitry Nov 19, 1995 Issued
Array ( [id] => 3733562 [patent_doc_number] => 05652528 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'Transceiver circuit and method of transmitting a signal which uses an output transistor to send data and assist in pulling up a bus' [patent_app_type] => 1 [patent_app_number] => 8/560368 [patent_app_country] => US [patent_app_date] => 1995-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6486 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652528.pdf [firstpage_image] =>[orig_patent_app_number] => 560368 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/560368
Transceiver circuit and method of transmitting a signal which uses an output transistor to send data and assist in pulling up a bus Nov 16, 1995 Issued
Array ( [id] => 3792340 [patent_doc_number] => 05736866 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Active pull-down circuit for ECL using a capacitive coupled circuit' [patent_app_type] => 1 [patent_app_number] => 8/555969 [patent_app_country] => US [patent_app_date] => 1995-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4452 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/736/05736866.pdf [firstpage_image] =>[orig_patent_app_number] => 555969 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/555969
Active pull-down circuit for ECL using a capacitive coupled circuit Nov 12, 1995 Issued
Array ( [id] => 3831602 [patent_doc_number] => 05731712 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Programmable gate array for relay ladder logic' [patent_app_type] => 1 [patent_app_number] => 8/555731 [patent_app_country] => US [patent_app_date] => 1995-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 6697 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 727 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/731/05731712.pdf [firstpage_image] =>[orig_patent_app_number] => 555731 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/555731
Programmable gate array for relay ladder logic Nov 8, 1995 Issued
Array ( [id] => 3737367 [patent_doc_number] => 05666068 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'GTL input receiver with hysteresis' [patent_app_type] => 1 [patent_app_number] => 8/552666 [patent_app_country] => US [patent_app_date] => 1995-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3311 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/666/05666068.pdf [firstpage_image] =>[orig_patent_app_number] => 552666 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/552666
GTL input receiver with hysteresis Nov 2, 1995 Issued
Array ( [id] => 3666942 [patent_doc_number] => 05648733 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Scan compatible 3-state bus control' [patent_app_type] => 1 [patent_app_number] => 8/548369 [patent_app_country] => US [patent_app_date] => 1995-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3569 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/648/05648733.pdf [firstpage_image] =>[orig_patent_app_number] => 548369 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/548369
Scan compatible 3-state bus control Oct 31, 1995 Issued
Array ( [id] => 3535666 [patent_doc_number] => 05583452 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Tri-directional buffer' [patent_app_type] => 1 [patent_app_number] => 8/548926 [patent_app_country] => US [patent_app_date] => 1995-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3892 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/583/05583452.pdf [firstpage_image] =>[orig_patent_app_number] => 548926 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/548926
Tri-directional buffer Oct 25, 1995 Issued
Array ( [id] => 3708606 [patent_doc_number] => 05675262 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Fast carry-out scheme in a field programmable gate array' [patent_app_type] => 1 [patent_app_number] => 8/548775 [patent_app_country] => US [patent_app_date] => 1995-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3367 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675262.pdf [firstpage_image] =>[orig_patent_app_number] => 548775 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/548775
Fast carry-out scheme in a field programmable gate array Oct 25, 1995 Issued
Array ( [id] => 3625949 [patent_doc_number] => 05614846 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-25 [patent_title] => 'Latch circuit with state-walk logic' [patent_app_type] => 1 [patent_app_number] => 8/548632 [patent_app_country] => US [patent_app_date] => 1995-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3073 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/614/05614846.pdf [firstpage_image] =>[orig_patent_app_number] => 548632 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/548632
Latch circuit with state-walk logic Oct 25, 1995 Issued
Array ( [id] => 3639591 [patent_doc_number] => 05631579 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-20 [patent_title] => 'Output buffer circuit for interfacing semiconductor integrated circuits operating on different supply voltages' [patent_app_type] => 1 [patent_app_number] => 8/548066 [patent_app_country] => US [patent_app_date] => 1995-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 8973 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/631/05631579.pdf [firstpage_image] =>[orig_patent_app_number] => 548066 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/548066
Output buffer circuit for interfacing semiconductor integrated circuits operating on different supply voltages Oct 24, 1995 Issued
Array ( [id] => 3707580 [patent_doc_number] => 05646555 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-08 [patent_title] => 'Pipeline structure using positive edge and negative edge flip-flops to decrease the size of a logic block' [patent_app_type] => 1 [patent_app_number] => 8/548167 [patent_app_country] => US [patent_app_date] => 1995-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 12994 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/646/05646555.pdf [firstpage_image] =>[orig_patent_app_number] => 548167 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/548167
Pipeline structure using positive edge and negative edge flip-flops to decrease the size of a logic block Oct 24, 1995 Issued
Array ( [id] => 3699765 [patent_doc_number] => 05650733 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-22 [patent_title] => 'Dynamic CMOS circuits with noise immunity' [patent_app_type] => 1 [patent_app_number] => 8/547269 [patent_app_country] => US [patent_app_date] => 1995-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1597 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/650/05650733.pdf [firstpage_image] =>[orig_patent_app_number] => 547269 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/547269
Dynamic CMOS circuits with noise immunity Oct 23, 1995 Issued
Array ( [id] => 3699955 [patent_doc_number] => 05680065 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Small computer system interface bus driving circuit with unique enable circuitry' [patent_app_type] => 1 [patent_app_number] => 8/545966 [patent_app_country] => US [patent_app_date] => 1995-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5071 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680065.pdf [firstpage_image] =>[orig_patent_app_number] => 545966 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/545966
Small computer system interface bus driving circuit with unique enable circuitry Oct 19, 1995 Issued
Array ( [id] => 3664416 [patent_doc_number] => 05592102 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices' [patent_app_type] => 1 [patent_app_number] => 8/545437 [patent_app_country] => US [patent_app_date] => 1995-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6853 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 434 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/592/05592102.pdf [firstpage_image] =>[orig_patent_app_number] => 545437 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/545437
Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices Oct 18, 1995 Issued
Array ( [id] => 3711838 [patent_doc_number] => 05654651 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'CMOS static logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/544730 [patent_app_country] => US [patent_app_date] => 1995-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 26 [patent_no_of_words] => 10879 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/654/05654651.pdf [firstpage_image] =>[orig_patent_app_number] => 544730 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/544730
CMOS static logic circuit Oct 17, 1995 Issued
Array ( [id] => 3521066 [patent_doc_number] => 05576634 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-19 [patent_title] => 'Bus driver for high-speed data transmission with waveform adjusting means' [patent_app_type] => 1 [patent_app_number] => 8/544581 [patent_app_country] => US [patent_app_date] => 1995-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 45 [patent_no_of_words] => 3859 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/576/05576634.pdf [firstpage_image] =>[orig_patent_app_number] => 544581 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/544581
Bus driver for high-speed data transmission with waveform adjusting means Oct 17, 1995 Issued
Array ( [id] => 3625670 [patent_doc_number] => 05642058 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-24 [patent_title] => 'Periphery input/output interconnect structure' [patent_app_type] => 1 [patent_app_number] => 8/543534 [patent_app_country] => US [patent_app_date] => 1995-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4981 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/642/05642058.pdf [firstpage_image] =>[orig_patent_app_number] => 543534 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/543534
Periphery input/output interconnect structure Oct 15, 1995 Issued
08/542366 LOGIC GATE HAVING TRANSMISSION GATE FOR ELECTRICALLY CONFIGURABLE DEVICE MULTIPLEXER Oct 11, 1995 Abandoned
Menu