Search

Benjamin Driscoll

Examiner (ID: 14622)

Most Active Art Unit
2509
Art Unit(s)
2878, 2509
Total Applications
368
Issued Applications
304
Pending Applications
18
Abandoned Applications
46

Applications

Application numberTitle of the applicationFiling DateStatus
08/542336 CMOS OUTPUT BUFFER CIRCUIT WHICH CONVERTS CMOS LOGIC SIGNALS TO ECL LOGIC SIGNALS AND WHICH DISCHARGES PARASITIC LOAD CAPACITANCES Oct 11, 1995 Abandoned
Array ( [id] => 3707411 [patent_doc_number] => 05646543 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-08 [patent_title] => 'Integrated circuit having reduced inductive noise' [patent_app_type] => 1 [patent_app_number] => 8/542242 [patent_app_country] => US [patent_app_date] => 1995-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6459 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/646/05646543.pdf [firstpage_image] =>[orig_patent_app_number] => 542242 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/542242
Integrated circuit having reduced inductive noise Oct 11, 1995 Issued
Array ( [id] => 3673370 [patent_doc_number] => 05600262 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-04 [patent_title] => 'Integrated circuit facilitating simultaneous programming of multiple antifuses' [patent_app_type] => 1 [patent_app_number] => 8/540726 [patent_app_country] => US [patent_app_date] => 1995-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 2857 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/600/05600262.pdf [firstpage_image] =>[orig_patent_app_number] => 540726 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/540726
Integrated circuit facilitating simultaneous programming of multiple antifuses Oct 10, 1995 Issued
Array ( [id] => 3699827 [patent_doc_number] => 05661412 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Reducing programming time of a field programmable gate array employing antifuses' [patent_app_type] => 1 [patent_app_number] => 8/541662 [patent_app_country] => US [patent_app_date] => 1995-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3732 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661412.pdf [firstpage_image] =>[orig_patent_app_number] => 541662 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/541662
Reducing programming time of a field programmable gate array employing antifuses Oct 9, 1995 Issued
Array ( [id] => 3608089 [patent_doc_number] => 05578946 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-26 [patent_title] => 'Input synchronization mechanism for inside/outside clock' [patent_app_type] => 1 [patent_app_number] => 8/539982 [patent_app_country] => US [patent_app_date] => 1995-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2960 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/578/05578946.pdf [firstpage_image] =>[orig_patent_app_number] => 539982 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/539982
Input synchronization mechanism for inside/outside clock Oct 5, 1995 Issued
Array ( [id] => 3733589 [patent_doc_number] => 05652530 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'Method and apparatus for reducing clock-data skew by clock shifting' [patent_app_type] => 1 [patent_app_number] => 8/536373 [patent_app_country] => US [patent_app_date] => 1995-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1920 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652530.pdf [firstpage_image] =>[orig_patent_app_number] => 536373 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/536373
Method and apparatus for reducing clock-data skew by clock shifting Sep 28, 1995 Issued
08/536267 TRISTATABLE OUTPUT DRIVER FOR USE WITH 3.3 OR 5 VOLT CMOS LOGIC Sep 28, 1995 Abandoned
Array ( [id] => 3863488 [patent_doc_number] => 05705942 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Method and apparatus for locating and improving critical speed paths in VLSI integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/537092 [patent_app_country] => US [patent_app_date] => 1995-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2462 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/705/05705942.pdf [firstpage_image] =>[orig_patent_app_number] => 537092 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/537092
Method and apparatus for locating and improving critical speed paths in VLSI integrated circuits Sep 28, 1995 Issued
Array ( [id] => 3687981 [patent_doc_number] => 05633600 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'Output buffer circuit having a minimized output voltage propagation' [patent_app_type] => 1 [patent_app_number] => 8/536780 [patent_app_country] => US [patent_app_date] => 1995-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3588 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/633/05633600.pdf [firstpage_image] =>[orig_patent_app_number] => 536780 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/536780
Output buffer circuit having a minimized output voltage propagation Sep 28, 1995 Issued
Array ( [id] => 3654136 [patent_doc_number] => 05640104 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-17 [patent_title] => 'Signal receiver in an interface' [patent_app_type] => 1 [patent_app_number] => 8/534030 [patent_app_country] => US [patent_app_date] => 1995-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 5814 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/640/05640104.pdf [firstpage_image] =>[orig_patent_app_number] => 534030 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/534030
Signal receiver in an interface Sep 25, 1995 Issued
Array ( [id] => 3885053 [patent_doc_number] => 05729155 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'High voltage CMOS circuit which protects the gate oxides from excessive voltages' [patent_app_type] => 1 [patent_app_number] => 8/531480 [patent_app_country] => US [patent_app_date] => 1995-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 11380 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/729/05729155.pdf [firstpage_image] =>[orig_patent_app_number] => 531480 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/531480
High voltage CMOS circuit which protects the gate oxides from excessive voltages Sep 20, 1995 Issued
Array ( [id] => 3688009 [patent_doc_number] => 05633602 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'Low voltage CMOS to low voltage PECL converter' [patent_app_type] => 1 [patent_app_number] => 8/528445 [patent_app_country] => US [patent_app_date] => 1995-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1845 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/633/05633602.pdf [firstpage_image] =>[orig_patent_app_number] => 528445 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/528445
Low voltage CMOS to low voltage PECL converter Sep 13, 1995 Issued
08/523068 OUTPUT BUFFER INCORPORATING SHARED INTERMEDIATE NODES Aug 31, 1995 Abandoned
Array ( [id] => 3699903 [patent_doc_number] => 05661417 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Bus system and bus sense amplifier with precharge means' [patent_app_type] => 1 [patent_app_number] => 8/521724 [patent_app_country] => US [patent_app_date] => 1995-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 12113 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661417.pdf [firstpage_image] =>[orig_patent_app_number] => 521724 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/521724
Bus system and bus sense amplifier with precharge means Aug 30, 1995 Issued
Array ( [id] => 3881445 [patent_doc_number] => 05764080 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Input/output interface circuitry for programmable logic array integrated circuit devices' [patent_app_type] => 1 [patent_app_number] => 8/519045 [patent_app_country] => US [patent_app_date] => 1995-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8325 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764080.pdf [firstpage_image] =>[orig_patent_app_number] => 519045 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/519045
Input/output interface circuitry for programmable logic array integrated circuit devices Aug 23, 1995 Issued
Array ( [id] => 3653281 [patent_doc_number] => 05629634 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'Low-power, tristate, off-chip driver circuit' [patent_app_type] => 1 [patent_app_number] => 8/517227 [patent_app_country] => US [patent_app_date] => 1995-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3631 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/629/05629634.pdf [firstpage_image] =>[orig_patent_app_number] => 517227 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/517227
Low-power, tristate, off-chip driver circuit Aug 20, 1995 Issued
Array ( [id] => 3905712 [patent_doc_number] => 05751165 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'High speed customizable logic array device' [patent_app_type] => 1 [patent_app_number] => 8/516739 [patent_app_country] => US [patent_app_date] => 1995-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 3107 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751165.pdf [firstpage_image] =>[orig_patent_app_number] => 516739 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/516739
High speed customizable logic array device Aug 17, 1995 Issued
08/512959 BICMOS TRI-STATE BUFFER WITH LOW LEAKAGE CURRENT Aug 8, 1995 Abandoned
08/508277 DEDICATED WIDE EXCLUSIVE OR FOR PLDS Jul 26, 1995 Abandoned
Array ( [id] => 3736609 [patent_doc_number] => 05635855 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-03 [patent_title] => 'Method for simultaneous programming of in-system programmable integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/505837 [patent_app_country] => US [patent_app_date] => 1995-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 7428 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/635/05635855.pdf [firstpage_image] =>[orig_patent_app_number] => 505837 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/505837
Method for simultaneous programming of in-system programmable integrated circuits Jul 20, 1995 Issued
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