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Benjamin Driscoll

Examiner (ID: 4258)

Most Active Art Unit
2509
Art Unit(s)
2509, 2878
Total Applications
368
Issued Applications
304
Pending Applications
18
Abandoned Applications
46

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3669983 [patent_doc_number] => 05598115 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'Comparator cell for use in a content addressable memory' [patent_app_type] => 1 [patent_app_number] => 8/385496 [patent_app_country] => US [patent_app_date] => 1995-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 9290 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/598/05598115.pdf [firstpage_image] =>[orig_patent_app_number] => 385496 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/385496
Comparator cell for use in a content addressable memory Feb 7, 1995 Issued
Array ( [id] => 3434325 [patent_doc_number] => 05463331 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-31 [patent_title] => 'Programmable slew rate CMOS buffer and transmission line driver with temperature compensation' [patent_app_type] => 1 [patent_app_number] => 8/384358 [patent_app_country] => US [patent_app_date] => 1995-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 13627 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/463/05463331.pdf [firstpage_image] =>[orig_patent_app_number] => 384358 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/384358
Programmable slew rate CMOS buffer and transmission line driver with temperature compensation Feb 1, 1995 Issued
Array ( [id] => 3558685 [patent_doc_number] => 05519339 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-21 [patent_title] => 'Complementary signal BiCMOS line driver with low skew' [patent_app_type] => 1 [patent_app_number] => 8/382952 [patent_app_country] => US [patent_app_date] => 1995-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2112 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/519/05519339.pdf [firstpage_image] =>[orig_patent_app_number] => 382952 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/382952
Complementary signal BiCMOS line driver with low skew Jan 31, 1995 Issued
Array ( [id] => 3557996 [patent_doc_number] => 05493239 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-20 [patent_title] => 'Circuit and method of configuring a field programmable gate array' [patent_app_type] => 1 [patent_app_number] => 8/381388 [patent_app_country] => US [patent_app_date] => 1995-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2073 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/493/05493239.pdf [firstpage_image] =>[orig_patent_app_number] => 381388 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/381388
Circuit and method of configuring a field programmable gate array Jan 30, 1995 Issued
Array ( [id] => 3617778 [patent_doc_number] => 05534791 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Noise isolated I/O buffer' [patent_app_type] => 1 [patent_app_number] => 8/375741 [patent_app_country] => US [patent_app_date] => 1995-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 8226 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/534/05534791.pdf [firstpage_image] =>[orig_patent_app_number] => 375741 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/375741
Noise isolated I/O buffer Jan 19, 1995 Issued
Array ( [id] => 3586923 [patent_doc_number] => 05498982 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-12 [patent_title] => 'High speed comparator with a precise sampling instant' [patent_app_type] => 1 [patent_app_number] => 8/374866 [patent_app_country] => US [patent_app_date] => 1995-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3203 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/498/05498982.pdf [firstpage_image] =>[orig_patent_app_number] => 374866 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/374866
High speed comparator with a precise sampling instant Jan 18, 1995 Issued
Array ( [id] => 3499966 [patent_doc_number] => 05508639 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-16 [patent_title] => 'CMOS clock drivers with inductive coupling' [patent_app_type] => 1 [patent_app_number] => 8/373694 [patent_app_country] => US [patent_app_date] => 1995-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2908 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/508/05508639.pdf [firstpage_image] =>[orig_patent_app_number] => 373694 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/373694
CMOS clock drivers with inductive coupling Jan 12, 1995 Issued
Array ( [id] => 3522850 [patent_doc_number] => 05506520 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-09 [patent_title] => 'Energy conserving clock pulse generating circuits' [patent_app_type] => 1 [patent_app_number] => 8/371191 [patent_app_country] => US [patent_app_date] => 1995-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 4160 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/506/05506520.pdf [firstpage_image] =>[orig_patent_app_number] => 371191 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/371191
Energy conserving clock pulse generating circuits Jan 10, 1995 Issued
Array ( [id] => 3587423 [patent_doc_number] => 05581199 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Interconnect architecture for field programmable gate array using variable length conductors' [patent_app_type] => 1 [patent_app_number] => 8/368692 [patent_app_country] => US [patent_app_date] => 1995-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 30 [patent_no_of_words] => 12501 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/581/05581199.pdf [firstpage_image] =>[orig_patent_app_number] => 368692 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/368692
Interconnect architecture for field programmable gate array using variable length conductors Jan 3, 1995 Issued
Array ( [id] => 3521135 [patent_doc_number] => 05576639 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-19 [patent_title] => 'BICMOS level shifter of a semiconductor integrated circuit and data output buffer using the same' [patent_app_type] => 1 [patent_app_number] => 8/368793 [patent_app_country] => US [patent_app_date] => 1995-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4116 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/576/05576639.pdf [firstpage_image] =>[orig_patent_app_number] => 368793 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/368793
BICMOS level shifter of a semiconductor integrated circuit and data output buffer using the same Jan 3, 1995 Issued
Array ( [id] => 3708634 [patent_doc_number] => 05675264 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Phase differential circuit having high synchronicity' [patent_app_type] => 1 [patent_app_number] => 8/364971 [patent_app_country] => US [patent_app_date] => 1994-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1847 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675264.pdf [firstpage_image] =>[orig_patent_app_number] => 364971 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/364971
Phase differential circuit having high synchronicity Dec 27, 1994 Issued
Array ( [id] => 3554707 [patent_doc_number] => 05548229 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-20 [patent_title] => 'Tri-state output buffer circuit' [patent_app_type] => 1 [patent_app_number] => 8/364105 [patent_app_country] => US [patent_app_date] => 1994-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10927 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/548/05548229.pdf [firstpage_image] =>[orig_patent_app_number] => 364105 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/364105
Tri-state output buffer circuit Dec 26, 1994 Issued
Array ( [id] => 3625883 [patent_doc_number] => 05614841 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-25 [patent_title] => 'Frequency multiplier using XOR/NXOR gates which have equal propagation delays' [patent_app_type] => 1 [patent_app_number] => 8/362892 [patent_app_country] => US [patent_app_date] => 1994-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4898 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/614/05614841.pdf [firstpage_image] =>[orig_patent_app_number] => 362892 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/362892
Frequency multiplier using XOR/NXOR gates which have equal propagation delays Dec 22, 1994 Issued
Array ( [id] => 3591960 [patent_doc_number] => 05552719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-03 [patent_title] => 'Output buffer circuit having gate voltage control circuit of gate current controlling transistor connected to output transistor' [patent_app_type] => 1 [patent_app_number] => 8/362896 [patent_app_country] => US [patent_app_date] => 1994-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4380 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/552/05552719.pdf [firstpage_image] =>[orig_patent_app_number] => 362896 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/362896
Output buffer circuit having gate voltage control circuit of gate current controlling transistor connected to output transistor Dec 22, 1994 Issued
Array ( [id] => 3485545 [patent_doc_number] => 05457403 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-10 [patent_title] => 'Fault tolerant and gate circuit' [patent_app_type] => 1 [patent_app_number] => 8/362096 [patent_app_country] => US [patent_app_date] => 1994-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1696 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/457/05457403.pdf [firstpage_image] =>[orig_patent_app_number] => 362096 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/362096
Fault tolerant and gate circuit Dec 21, 1994 Issued
Array ( [id] => 3619780 [patent_doc_number] => 05510731 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-23 [patent_title] => 'Level translator with a voltage shifting element' [patent_app_type] => 1 [patent_app_number] => 8/357896 [patent_app_country] => US [patent_app_date] => 1994-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3365 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/510/05510731.pdf [firstpage_image] =>[orig_patent_app_number] => 357896 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/357896
Level translator with a voltage shifting element Dec 15, 1994 Issued
Array ( [id] => 3532173 [patent_doc_number] => 05541535 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-30 [patent_title] => 'CMOS simultaneous transmission bidirectional driver/receiver' [patent_app_type] => 1 [patent_app_number] => 8/357885 [patent_app_country] => US [patent_app_date] => 1994-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5868 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/541/05541535.pdf [firstpage_image] =>[orig_patent_app_number] => 357885 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/357885
CMOS simultaneous transmission bidirectional driver/receiver Dec 15, 1994 Issued
Array ( [id] => 3697351 [patent_doc_number] => 05696729 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Power reducing circuit for synchronous semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/356725 [patent_app_country] => US [patent_app_date] => 1994-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3305 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696729.pdf [firstpage_image] =>[orig_patent_app_number] => 356725 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/356725
Power reducing circuit for synchronous semiconductor device Dec 14, 1994 Issued
Array ( [id] => 3572079 [patent_doc_number] => 05485103 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-16 [patent_title] => 'Programmable logic array with local and global conductors' [patent_app_type] => 1 [patent_app_number] => 8/356516 [patent_app_country] => US [patent_app_date] => 1994-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3419 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/485/05485103.pdf [firstpage_image] =>[orig_patent_app_number] => 356516 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/356516
Programmable logic array with local and global conductors Dec 14, 1994 Issued
Array ( [id] => 3737474 [patent_doc_number] => 05694060 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'CMOS differential twisted-pair driver' [patent_app_type] => 1 [patent_app_number] => 8/355428 [patent_app_country] => US [patent_app_date] => 1994-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 2520 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694060.pdf [firstpage_image] =>[orig_patent_app_number] => 355428 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/355428
CMOS differential twisted-pair driver Dec 12, 1994 Issued
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