Search

Benjamin E. Lanier

Examiner (ID: 11317, Phone: (571)272-3805 , Office: P/2437 )

Most Active Art Unit
2437
Art Unit(s)
2437, 2132, 2432
Total Applications
1337
Issued Applications
871
Pending Applications
110
Abandoned Applications
371

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14722969 [patent_doc_number] => 20190252548 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2019-08-15 [patent_title] => EMBEDDED SOURCE/DRAIN STRUCTURE FOR TALL FINFET AND METHOD OF FORMATION [patent_app_type] => utility [patent_app_number] => 15/672586 [patent_app_country] => US [patent_app_date] => 2017-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3771 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15672586 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/672586
Embedded source/drain structure for tall FinFET and method of formation Aug 8, 2017 Issued
Array ( [id] => 14722969 [patent_doc_number] => 20190252548 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2019-08-15 [patent_title] => EMBEDDED SOURCE/DRAIN STRUCTURE FOR TALL FINFET AND METHOD OF FORMATION [patent_app_type] => utility [patent_app_number] => 15/672586 [patent_app_country] => US [patent_app_date] => 2017-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3771 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15672586 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/672586
Embedded source/drain structure for tall FinFET and method of formation Aug 8, 2017 Issued
Array ( [id] => 13057051 [patent_doc_number] => 10049922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-14 [patent_title] => Method of forming trenches [patent_app_type] => utility [patent_app_number] => 15/670000 [patent_app_country] => US [patent_app_date] => 2017-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4614 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15670000 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/670000
Method of forming trenches Aug 6, 2017 Issued
Array ( [id] => 12181754 [patent_doc_number] => 20180040690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/669168 [patent_app_country] => US [patent_app_date] => 2017-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4612 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15669168 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/669168
Semiconductor device and method of manufacturing semiconductor device Aug 3, 2017 Issued
Array ( [id] => 12457767 [patent_doc_number] => 09985128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-29 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/667895 [patent_app_country] => US [patent_app_date] => 2017-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 42 [patent_no_of_words] => 14477 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 380 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15667895 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/667895
Semiconductor device Aug 2, 2017 Issued
Array ( [id] => 14125911 [patent_doc_number] => 10249821 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Formation and structure of lyotropic liquid crystalline mesophases in donor-acceptor semiconducting polymers [patent_app_type] => utility [patent_app_number] => 15/661442 [patent_app_country] => US [patent_app_date] => 2017-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 61 [patent_no_of_words] => 22392 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15661442 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/661442
Formation and structure of lyotropic liquid crystalline mesophases in donor-acceptor semiconducting polymers Jul 26, 2017 Issued
Array ( [id] => 13085277 [patent_doc_number] => 10062712 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-28 [patent_title] => Method to fabricate both FD-SOI and PD-SOI devices within a single integrated circuit [patent_app_type] => utility [patent_app_number] => 15/660104 [patent_app_country] => US [patent_app_date] => 2017-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 4889 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15660104 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/660104
Method to fabricate both FD-SOI and PD-SOI devices within a single integrated circuit Jul 25, 2017 Issued
Array ( [id] => 13043369 [patent_doc_number] => 10043826 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-07 [patent_title] => Fully depleted silicon on insulator integration [patent_app_type] => utility [patent_app_number] => 15/660288 [patent_app_country] => US [patent_app_date] => 2017-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 37 [patent_no_of_words] => 4137 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15660288 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/660288
Fully depleted silicon on insulator integration Jul 25, 2017 Issued
Array ( [id] => 13293147 [patent_doc_number] => 10157774 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-18 [patent_title] => Contact scheme for landing on different contact area levels [patent_app_type] => utility [patent_app_number] => 15/658570 [patent_app_country] => US [patent_app_date] => 2017-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 2711 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15658570 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/658570
Contact scheme for landing on different contact area levels Jul 24, 2017 Issued
Array ( [id] => 13879095 [patent_doc_number] => 20190035888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => NANOSHEET FIELD-EFFECT TRANSISTOR WITH SELF-ALIGNED SOURCE/DRAIN ISOLATION [patent_app_type] => utility [patent_app_number] => 15/658943 [patent_app_country] => US [patent_app_date] => 2017-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3336 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15658943 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/658943
NANOSHEET FIELD-EFFECT TRANSISTOR WITH SELF-ALIGNED SOURCE/DRAIN ISOLATION Jul 24, 2017 Abandoned
Array ( [id] => 15077659 [patent_doc_number] => 10468329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Thermally enhanced semiconductor package having field effect transistors with back-gate feature [patent_app_type] => utility [patent_app_number] => 15/652826 [patent_app_country] => US [patent_app_date] => 2017-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 5509 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15652826 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/652826
Thermally enhanced semiconductor package having field effect transistors with back-gate feature Jul 17, 2017 Issued
Array ( [id] => 15077659 [patent_doc_number] => 10468329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Thermally enhanced semiconductor package having field effect transistors with back-gate feature [patent_app_type] => utility [patent_app_number] => 15/652826 [patent_app_country] => US [patent_app_date] => 2017-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 5509 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15652826 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/652826
Thermally enhanced semiconductor package having field effect transistors with back-gate feature Jul 17, 2017 Issued
Array ( [id] => 12141102 [patent_doc_number] => 20180019185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'THERMALLY ENHANCED SEMICONDUCTOR PACKAGE HAVING FIELD EFFECT TRANSISTORS WITH BACK-GATE FEATURE' [patent_app_type] => utility [patent_app_number] => 15/652867 [patent_app_country] => US [patent_app_date] => 2017-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5786 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15652867 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/652867
Thermally enhanced semiconductor package having field effect transistors with back-gate feature Jul 17, 2017 Issued
Array ( [id] => 15077659 [patent_doc_number] => 10468329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Thermally enhanced semiconductor package having field effect transistors with back-gate feature [patent_app_type] => utility [patent_app_number] => 15/652826 [patent_app_country] => US [patent_app_date] => 2017-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 5509 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15652826 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/652826
Thermally enhanced semiconductor package having field effect transistors with back-gate feature Jul 17, 2017 Issued
Array ( [id] => 15077659 [patent_doc_number] => 10468329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Thermally enhanced semiconductor package having field effect transistors with back-gate feature [patent_app_type] => utility [patent_app_number] => 15/652826 [patent_app_country] => US [patent_app_date] => 2017-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 5509 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15652826 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/652826
Thermally enhanced semiconductor package having field effect transistors with back-gate feature Jul 17, 2017 Issued
Array ( [id] => 15077659 [patent_doc_number] => 10468329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Thermally enhanced semiconductor package having field effect transistors with back-gate feature [patent_app_type] => utility [patent_app_number] => 15/652826 [patent_app_country] => US [patent_app_date] => 2017-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 5509 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15652826 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/652826
Thermally enhanced semiconductor package having field effect transistors with back-gate feature Jul 17, 2017 Issued
Array ( [id] => 12141102 [patent_doc_number] => 20180019185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'THERMALLY ENHANCED SEMICONDUCTOR PACKAGE HAVING FIELD EFFECT TRANSISTORS WITH BACK-GATE FEATURE' [patent_app_type] => utility [patent_app_number] => 15/652867 [patent_app_country] => US [patent_app_date] => 2017-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5786 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15652867 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/652867
Thermally enhanced semiconductor package having field effect transistors with back-gate feature Jul 17, 2017 Issued
Array ( [id] => 15077659 [patent_doc_number] => 10468329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Thermally enhanced semiconductor package having field effect transistors with back-gate feature [patent_app_type] => utility [patent_app_number] => 15/652826 [patent_app_country] => US [patent_app_date] => 2017-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 5509 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15652826 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/652826
Thermally enhanced semiconductor package having field effect transistors with back-gate feature Jul 17, 2017 Issued
Array ( [id] => 15077659 [patent_doc_number] => 10468329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Thermally enhanced semiconductor package having field effect transistors with back-gate feature [patent_app_type] => utility [patent_app_number] => 15/652826 [patent_app_country] => US [patent_app_date] => 2017-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 5509 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15652826 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/652826
Thermally enhanced semiconductor package having field effect transistors with back-gate feature Jul 17, 2017 Issued
Array ( [id] => 15077659 [patent_doc_number] => 10468329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Thermally enhanced semiconductor package having field effect transistors with back-gate feature [patent_app_type] => utility [patent_app_number] => 15/652826 [patent_app_country] => US [patent_app_date] => 2017-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 5509 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15652826 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/652826
Thermally enhanced semiconductor package having field effect transistors with back-gate feature Jul 17, 2017 Issued
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