
Benjamin E. Lanier
Examiner (ID: 11317, Phone: (571)272-3805 , Office: P/2437 )
| Most Active Art Unit | 2437 |
| Art Unit(s) | 2437, 2132, 2432 |
| Total Applications | 1337 |
| Issued Applications | 871 |
| Pending Applications | 110 |
| Abandoned Applications | 371 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16645713
[patent_doc_number] => 10923581
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-16
[patent_title] => Method for forming semiconductor structure
[patent_app_type] => utility
[patent_app_number] => 16/695650
[patent_app_country] => US
[patent_app_date] => 2019-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 8189
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16695650
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/695650 | Method for forming semiconductor structure | Nov 25, 2019 | Issued |
Array
(
[id] => 16264534
[patent_doc_number] => 10755978
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-08-25
[patent_title] => Shared contact structure and methods for forming the same
[patent_app_type] => utility
[patent_app_number] => 16/691801
[patent_app_country] => US
[patent_app_date] => 2019-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 10729
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16691801
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/691801 | Shared contact structure and methods for forming the same | Nov 21, 2019 | Issued |
Array
(
[id] => 16739124
[patent_doc_number] => 10964792
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-03-30
[patent_title] => Dual metal capped via contact structures for semiconductor devices
[patent_app_type] => utility
[patent_app_number] => 16/692127
[patent_app_country] => US
[patent_app_date] => 2019-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 12804
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16692127
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/692127 | Dual metal capped via contact structures for semiconductor devices | Nov 21, 2019 | Issued |
Array
(
[id] => 16684294
[patent_doc_number] => 10943784
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-09
[patent_title] => Method for optimizing a critical dimension for double patterning for NAND flash
[patent_app_type] => utility
[patent_app_number] => 16/684918
[patent_app_country] => US
[patent_app_date] => 2019-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 15
[patent_no_of_words] => 5602
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684918
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/684918 | Method for optimizing a critical dimension for double patterning for NAND flash | Nov 14, 2019 | Issued |
Array
(
[id] => 16048481
[patent_doc_number] => 10686126
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-16
[patent_title] => Back end of line metallization structures
[patent_app_type] => utility
[patent_app_number] => 16/681981
[patent_app_country] => US
[patent_app_date] => 2019-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 14
[patent_no_of_words] => 5297
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 264
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16681981
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/681981 | Back end of line metallization structures | Nov 12, 2019 | Issued |
Array
(
[id] => 16578821
[patent_doc_number] => 20210013222
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-14
[patent_title] => SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/678713
[patent_app_country] => US
[patent_app_date] => 2019-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7736
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16678713
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/678713 | Semiconductor device and a method of manufacturing a semiconductor device | Nov 7, 2019 | Issued |
Array
(
[id] => 15823205
[patent_doc_number] => 10636798
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-04-28
[patent_title] => Semiconductor device and method for fabricating the same
[patent_app_type] => utility
[patent_app_number] => 16/658170
[patent_app_country] => US
[patent_app_date] => 2019-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3549
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16658170
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/658170 | Semiconductor device and method for fabricating the same | Oct 20, 2019 | Issued |
Array
(
[id] => 15503619
[patent_doc_number] => 20200051998
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-13
[patent_title] => THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/657520
[patent_app_country] => US
[patent_app_date] => 2019-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8960
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16657520
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/657520 | Three-dimensional semiconductor device | Oct 17, 2019 | Issued |
Array
(
[id] => 16201931
[patent_doc_number] => 10727110
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-28
[patent_title] => Semiconductor device and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 16/594312
[patent_app_country] => US
[patent_app_date] => 2019-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 56
[patent_no_of_words] => 10178
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16594312
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/594312 | Semiconductor device and method of manufacturing the same | Oct 6, 2019 | Issued |
Array
(
[id] => 16502447
[patent_doc_number] => 10867841
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-15
[patent_title] => Semiconductor device and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 16/594278
[patent_app_country] => US
[patent_app_date] => 2019-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 56
[patent_no_of_words] => 10178
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16594278
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/594278 | Semiconductor device and method of manufacturing the same | Oct 6, 2019 | Issued |
Array
(
[id] => 15351579
[patent_doc_number] => 20200013681
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-09
[patent_title] => SELF-ALIGNED SILICIDE/GERMANIDE FORMATION TO REDUCE EXTERNAL RESISTANCE IN A VERTICAL FIELD-EFFECT TRANSISTOR
[patent_app_type] => utility
[patent_app_number] => 16/575796
[patent_app_country] => US
[patent_app_date] => 2019-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9735
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16575796
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/575796 | Self-aligned silicide/germanide formation to reduce external resistance in a vertical field-effect transistor | Sep 18, 2019 | Issued |
Array
(
[id] => 16700120
[patent_doc_number] => 10950731
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-03-16
[patent_title] => Inner spacers for gate-all-around semiconductor devices
[patent_app_type] => utility
[patent_app_number] => 16/572679
[patent_app_country] => US
[patent_app_date] => 2019-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 15
[patent_no_of_words] => 9633
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16572679
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/572679 | Inner spacers for gate-all-around semiconductor devices | Sep 16, 2019 | Issued |
Array
(
[id] => 16593866
[patent_doc_number] => 10903143
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-01-26
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 16/572627
[patent_app_country] => US
[patent_app_date] => 2019-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 14
[patent_no_of_words] => 6756
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 263
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16572627
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/572627 | Semiconductor device | Sep 16, 2019 | Issued |
Array
(
[id] => 16715727
[patent_doc_number] => 20210082874
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-18
[patent_title] => PACKAGE AND MANUFACTURING METHOD OF RECONSTRUCTED WAFER
[patent_app_type] => utility
[patent_app_number] => 16/572622
[patent_app_country] => US
[patent_app_date] => 2019-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10617
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16572622
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/572622 | Package and manufacturing method of reconstructed wafer | Sep 16, 2019 | Issued |
Array
(
[id] => 15332453
[patent_doc_number] => 20200006556
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-02
[patent_title] => Asymmetric Source and Drain Structures in Semiconductor Devices
[patent_app_type] => utility
[patent_app_number] => 16/569773
[patent_app_country] => US
[patent_app_date] => 2019-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10854
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16569773
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/569773 | Asymmetric source and drain structures in semiconductor devices | Sep 12, 2019 | Issued |
Array
(
[id] => 16418101
[patent_doc_number] => 10826004
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-11-03
[patent_title] => Flexible display panel and display apparatus
[patent_app_type] => utility
[patent_app_number] => 16/567099
[patent_app_country] => US
[patent_app_date] => 2019-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 5311
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16567099
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/567099 | Flexible display panel and display apparatus | Sep 10, 2019 | Issued |
Array
(
[id] => 15625603
[patent_doc_number] => 20200083206
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-12
[patent_title] => LIGHT EMITTING DIODE DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/566897
[patent_app_country] => US
[patent_app_date] => 2019-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4076
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566897
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/566897 | Light emitting diode display apparatus and manufacturing method thereof | Sep 10, 2019 | Issued |
Array
(
[id] => 16222954
[patent_doc_number] => 20200248070
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-06
[patent_title] => PEROVSKITE LUMINESCENT NANOCRYSTAL, LIGHT EMITTING DEVICE, AND MANUFACTURING METHOD FOR PEROVSKITE LUMINESCENT NANOCRYSTAL
[patent_app_type] => utility
[patent_app_number] => 16/566903
[patent_app_country] => US
[patent_app_date] => 2019-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6155
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566903
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/566903 | Perovskite luminescent nanocrystal, light emitting device, and manufacturing method for perovskite luminescent nanocrystal | Sep 10, 2019 | Issued |
Array
(
[id] => 16226445
[patent_doc_number] => 20200251562
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-06
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/566997
[patent_app_country] => US
[patent_app_date] => 2019-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5784
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566997
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/566997 | Semiconductor device and method for manufacturing the same | Sep 10, 2019 | Issued |
Array
(
[id] => 16249630
[patent_doc_number] => 10749006
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-08-18
[patent_title] => Trench power transistor and method of producing the same
[patent_app_type] => utility
[patent_app_number] => 16/567075
[patent_app_country] => US
[patent_app_date] => 2019-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6606
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 377
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16567075
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/567075 | Trench power transistor and method of producing the same | Sep 10, 2019 | Issued |