Search

Benjamin E. Lanier

Examiner (ID: 11317, Phone: (571)272-3805 , Office: P/2437 )

Most Active Art Unit
2437
Art Unit(s)
2437, 2132, 2432
Total Applications
1337
Issued Applications
871
Pending Applications
110
Abandoned Applications
371

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10502521 [patent_doc_number] => 09230922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'Precursor composition for deposition of silicon dioxide film and method for fabricating semiconductor device using the same' [patent_app_type] => utility [patent_app_number] => 14/180907 [patent_app_country] => US [patent_app_date] => 2014-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 7456 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14180907 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/180907
Precursor composition for deposition of silicon dioxide film and method for fabricating semiconductor device using the same Feb 13, 2014 Issued
Array ( [id] => 10909455 [patent_doc_number] => 20140312471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-23 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/179847 [patent_app_country] => US [patent_app_date] => 2014-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3432 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14179847 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/179847
Semiconductor device and manufacturing method thereof Feb 12, 2014 Issued
Array ( [id] => 9768155 [patent_doc_number] => 20140291817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-02 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING POROUS LOW-K DIELECTRIC LAYER AND FABRICATION METHOD' [patent_app_type] => utility [patent_app_number] => 14/178494 [patent_app_country] => US [patent_app_date] => 2014-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5111 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14178494 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/178494
Semiconductor device including porous low-k dielectric layer and fabrication method Feb 11, 2014 Issued
Array ( [id] => 9882395 [patent_doc_number] => 08969158 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-03 [patent_title] => 'Vertical gate LDMOS device' [patent_app_type] => utility [patent_app_number] => 14/166659 [patent_app_country] => US [patent_app_date] => 2014-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 84 [patent_no_of_words] => 16113 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14166659 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/166659
Vertical gate LDMOS device Jan 27, 2014 Issued
Array ( [id] => 9631951 [patent_doc_number] => 20140210058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-31 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/166722 [patent_app_country] => US [patent_app_date] => 2014-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8559 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14166722 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/166722
Semiconductor device and method of fabricating the same Jan 27, 2014 Issued
Array ( [id] => 10909473 [patent_doc_number] => 20140312489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-23 [patent_title] => 'FLIP-CHIP SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/155697 [patent_app_country] => US [patent_app_date] => 2014-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6986 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14155697 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/155697
FLIP-CHIP SEMICONDUCTOR PACKAGE Jan 14, 2014 Abandoned
Array ( [id] => 10060156 [patent_doc_number] => 09099520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-04 [patent_title] => 'Insulated gate bipolar transistor' [patent_app_type] => utility [patent_app_number] => 14/154790 [patent_app_country] => US [patent_app_date] => 2014-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 9099 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 415 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14154790 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/154790
Insulated gate bipolar transistor Jan 13, 2014 Issued
Array ( [id] => 10118787 [patent_doc_number] => 09153676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-06 [patent_title] => 'Insulated gate bipolar transistor' [patent_app_type] => utility [patent_app_number] => 14/154736 [patent_app_country] => US [patent_app_date] => 2014-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 8916 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 475 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14154736 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/154736
Insulated gate bipolar transistor Jan 13, 2014 Issued
Array ( [id] => 9600854 [patent_doc_number] => 20140197536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-17 [patent_title] => 'PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THEREOF' [patent_app_type] => utility [patent_app_number] => 14/152970 [patent_app_country] => US [patent_app_date] => 2014-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3560 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14152970 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/152970
Package structure and method for manufacturing thereof Jan 9, 2014 Issued
Array ( [id] => 9460515 [patent_doc_number] => 20140124941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/149890 [patent_app_country] => US [patent_app_date] => 2014-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8739 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14149890 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/149890
Semiconductor device Jan 7, 2014 Issued
Array ( [id] => 9460404 [patent_doc_number] => 20140124829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'INSULATED GATE BIPOLAR TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 14/149412 [patent_app_country] => US [patent_app_date] => 2014-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6146 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14149412 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/149412
Insulated gate bipolar transistor Jan 6, 2014 Issued
Array ( [id] => 9977405 [patent_doc_number] => 09023716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-05 [patent_title] => 'Methods for processing substrates' [patent_app_type] => utility [patent_app_number] => 14/147718 [patent_app_country] => US [patent_app_date] => 2014-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 30 [patent_no_of_words] => 7538 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14147718 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/147718
Methods for processing substrates Jan 5, 2014 Issued
Array ( [id] => 9566015 [patent_doc_number] => 20140183728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'WAFER SUPPORTING STRUCTURE, INTERMEDIATE STRUCTURE OF A SEMICONDUCTOR PACKAGE INCLUDING THE WAFER SUPPORTING STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/147051 [patent_app_country] => US [patent_app_date] => 2014-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6199 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14147051 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/147051
Wafer supporting structure, intermediate structure of a semiconductor package including the wafer supporting structure Jan 2, 2014 Issued
Array ( [id] => 10518799 [patent_doc_number] => 09245853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-26 [patent_title] => 'Memory module' [patent_app_type] => utility [patent_app_number] => 14/140725 [patent_app_country] => US [patent_app_date] => 2013-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 4788 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14140725 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/140725
Memory module Dec 25, 2013 Issued
Array ( [id] => 9754089 [patent_doc_number] => 20140284789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/139948 [patent_app_country] => US [patent_app_date] => 2013-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11769 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14139948 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/139948
Method of manufacturing semiconductor device and semiconductor device Dec 23, 2013 Issued
Array ( [id] => 10112243 [patent_doc_number] => 09147662 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-09-29 [patent_title] => 'Integrated circuit packaging system with fiber-less substrate and method of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 14/137755 [patent_app_country] => US [patent_app_date] => 2013-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 6502 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14137755 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/137755
Integrated circuit packaging system with fiber-less substrate and method of manufacture thereof Dec 19, 2013 Issued
Array ( [id] => 10597581 [patent_doc_number] => 09318678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-19 [patent_title] => 'Reflecto trough for an optoelectronic semiconductor component' [patent_app_type] => utility [patent_app_number] => 14/653835 [patent_app_country] => US [patent_app_date] => 2013-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4958 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14653835 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/653835
Reflecto trough for an optoelectronic semiconductor component Dec 15, 2013 Issued
Array ( [id] => 9542610 [patent_doc_number] => 20140167257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'FABRICATION OF THREE-DIMENSIONAL HIGH SURFACE AREA ELECTRODES' [patent_app_type] => utility [patent_app_number] => 14/106701 [patent_app_country] => US [patent_app_date] => 2013-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 6371 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14106701 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/106701
Fabrication of three-dimensional high surface area electrodes Dec 12, 2013 Issued
Array ( [id] => 10066742 [patent_doc_number] => 09105601 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-11 [patent_title] => 'Power module package' [patent_app_type] => utility [patent_app_number] => 14/106107 [patent_app_country] => US [patent_app_date] => 2013-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4367 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14106107 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/106107
Power module package Dec 12, 2013 Issued
Array ( [id] => 9557934 [patent_doc_number] => 20140175646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 14/101352 [patent_app_country] => US [patent_app_date] => 2013-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3568 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14101352 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/101352
Package structure and method for manufacturing same Dec 9, 2013 Issued
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