
Benjamin E. Lanier
Examiner (ID: 11317, Phone: (571)272-3805 , Office: P/2437 )
| Most Active Art Unit | 2437 |
| Art Unit(s) | 2437, 2132, 2432 |
| Total Applications | 1337 |
| Issued Applications | 871 |
| Pending Applications | 110 |
| Abandoned Applications | 371 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10512950
[patent_doc_number] => 09240530
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-01-19
[patent_title] => 'Light emitter devices having improved chemical and physical resistance and related methods'
[patent_app_type] => utility
[patent_app_number] => 13/444394
[patent_app_country] => US
[patent_app_date] => 2012-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 12459
[patent_no_of_claims] => 54
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13444394
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/444394 | Light emitter devices having improved chemical and physical resistance and related methods | Apr 10, 2012 | Issued |
Array
(
[id] => 10651401
[patent_doc_number] => 09367655
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-06-14
[patent_title] => 'Topography-aware lithography pattern check'
[patent_app_type] => utility
[patent_app_number] => 13/443568
[patent_app_country] => US
[patent_app_date] => 2012-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5457
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13443568
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/443568 | Topography-aware lithography pattern check | Apr 9, 2012 | Issued |
Array
(
[id] => 9166578
[patent_doc_number] => 08592255
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-11-26
[patent_title] => 'Method for electrically connecting dual silicon-on-insulator device layers'
[patent_app_type] => utility
[patent_app_number] => 13/442454
[patent_app_country] => US
[patent_app_date] => 2012-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2837
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13442454
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/442454 | Method for electrically connecting dual silicon-on-insulator device layers | Apr 8, 2012 | Issued |
Array
(
[id] => 8955745
[patent_doc_number] => 08501517
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-08-06
[patent_title] => 'Method of assembling pressure sensor device'
[patent_app_type] => utility
[patent_app_number] => 13/441928
[patent_app_country] => US
[patent_app_date] => 2012-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 14
[patent_no_of_words] => 3508
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13441928
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/441928 | Method of assembling pressure sensor device | Apr 8, 2012 | Issued |
Array
(
[id] => 9059724
[patent_doc_number] => 08546160
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-10-01
[patent_title] => 'Method for packaging light emitting diodes'
[patent_app_type] => utility
[patent_app_number] => 13/441934
[patent_app_country] => US
[patent_app_date] => 2012-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 1444
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 307
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13441934
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/441934 | Method for packaging light emitting diodes | Apr 8, 2012 | Issued |
Array
(
[id] => 8904283
[patent_doc_number] => 20130171786
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-07-04
[patent_title] => 'NON-VOLATILE MEMORY (NVM) AND LOGIC INTEGRATION'
[patent_app_type] => utility
[patent_app_number] => 13/441426
[patent_app_country] => US
[patent_app_date] => 2012-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4876
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13441426
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/441426 | Non-volatile memory (NVM) and logic integration | Apr 5, 2012 | Issued |
Array
(
[id] => 9882417
[patent_doc_number] => 08969181
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-03-03
[patent_title] => 'Method for epitaxial layer overgrowth'
[patent_app_type] => utility
[patent_app_number] => 13/440616
[patent_app_country] => US
[patent_app_date] => 2012-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3119
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13440616
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/440616 | Method for epitaxial layer overgrowth | Apr 4, 2012 | Issued |
Array
(
[id] => 9081547
[patent_doc_number] => 20130267077
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-10
[patent_title] => 'METHOD AND SYSTEM FOR MANUFACTURING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/439888
[patent_app_country] => US
[patent_app_date] => 2012-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5731
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13439888
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/439888 | Method and system for manufacturing semiconductor device | Apr 4, 2012 | Issued |
Array
(
[id] => 10844437
[patent_doc_number] => 08871612
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-10-28
[patent_title] => 'Method for forming a cleaved facet of semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 13/440640
[patent_app_country] => US
[patent_app_date] => 2012-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 6664
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13440640
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/440640 | Method for forming a cleaved facet of semiconductor device | Apr 4, 2012 | Issued |
Array
(
[id] => 9676811
[patent_doc_number] => 08815720
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-08-26
[patent_title] => 'Method of etching a workpiece'
[patent_app_type] => utility
[patent_app_number] => 13/440678
[patent_app_country] => US
[patent_app_date] => 2012-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 4
[patent_no_of_words] => 3133
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13440678
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/440678 | Method of etching a workpiece | Apr 4, 2012 | Issued |
Array
(
[id] => 9112968
[patent_doc_number] => 08569136
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-10-29
[patent_title] => 'Manufacturing method of semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 13/438972
[patent_app_country] => US
[patent_app_date] => 2012-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 69
[patent_figures_cnt] => 81
[patent_no_of_words] => 37064
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 319
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13438972
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/438972 | Manufacturing method of semiconductor device | Apr 3, 2012 | Issued |
Array
(
[id] => 8612324
[patent_doc_number] => 20130017636
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-17
[patent_title] => 'COMPOSITION FOR REMOVING A PHOTORESIST AND METHOD OF MANUFACTURING A THIN-FILM TRANSISTOR SUBSTRATE USING THE COMPOSITION'
[patent_app_type] => utility
[patent_app_number] => 13/439418
[patent_app_country] => US
[patent_app_date] => 2012-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 10665
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13439418
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/439418 | Composition for removing a photoresist and method of manufacturing a thin-film transistor substrate using the composition | Apr 3, 2012 | Issued |
Array
(
[id] => 9323470
[patent_doc_number] => 08658490
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-02-25
[patent_title] => 'Passivating point defects in high-K gate dielectric layers during gate stack formation'
[patent_app_type] => utility
[patent_app_number] => 13/439016
[patent_app_country] => US
[patent_app_date] => 2012-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 8213
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13439016
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/439016 | Passivating point defects in high-K gate dielectric layers during gate stack formation | Apr 3, 2012 | Issued |
Array
(
[id] => 8767603
[patent_doc_number] => 20130095640
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-04-18
[patent_title] => 'REUSABLE SUBSTRATES FOR ELECTRONIC DEVICE FABRICATION AND METHODS THEREOF'
[patent_app_type] => utility
[patent_app_number] => 13/439677
[patent_app_country] => US
[patent_app_date] => 2012-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7317
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13439677
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/439677 | Reusable substrates for electronic device fabrication and methods thereof | Apr 3, 2012 | Issued |
Array
(
[id] => 9311692
[patent_doc_number] => 08652910
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-02-18
[patent_title] => 'Method for fabricating semiconductor device and device using same'
[patent_app_type] => utility
[patent_app_number] => 13/438250
[patent_app_country] => US
[patent_app_date] => 2012-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 6097
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13438250
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/438250 | Method for fabricating semiconductor device and device using same | Apr 2, 2012 | Issued |
Array
(
[id] => 9068792
[patent_doc_number] => 20130260548
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-03
[patent_title] => 'TECHNIQUES FOR USING MATERIAL SUBSTITUTION PROCESSES TO FORM REPLACEMENT METAL GATE ELECTRODES OF SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACTS'
[patent_app_type] => utility
[patent_app_number] => 13/438394
[patent_app_country] => US
[patent_app_date] => 2012-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 12351
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13438394
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/438394 | Techniques for using material substitution processes to form replacement metal gate electrodes of semiconductor devices with self-aligned contacts | Apr 2, 2012 | Issued |
Array
(
[id] => 8441941
[patent_doc_number] => 20120258556
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-10-11
[patent_title] => 'METHOD FOR MANUFACTURING LIQUID EJECTING HEAD'
[patent_app_type] => utility
[patent_app_number] => 13/438150
[patent_app_country] => US
[patent_app_date] => 2012-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5665
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13438150
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/438150 | Method for manufacturing liquid ejecting head | Apr 2, 2012 | Issued |
Array
(
[id] => 9254511
[patent_doc_number] => 08617923
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-12-31
[patent_title] => 'Semiconductor device manufacturing apparatus and method for manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 13/438482
[patent_app_country] => US
[patent_app_date] => 2012-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 31
[patent_no_of_words] => 14959
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13438482
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/438482 | Semiconductor device manufacturing apparatus and method for manufacturing semiconductor device | Apr 2, 2012 | Issued |
Array
(
[id] => 9127090
[patent_doc_number] => 08575039
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-11-05
[patent_title] => 'Surface treating method and film depositing method'
[patent_app_type] => utility
[patent_app_number] => 13/425514
[patent_app_country] => US
[patent_app_date] => 2012-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 19
[patent_no_of_words] => 11695
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13425514
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/425514 | Surface treating method and film depositing method | Mar 20, 2012 | Issued |
Array
(
[id] => 8393732
[patent_doc_number] => 20120231572
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-09-13
[patent_title] => 'METHOD FOR FABRICATING NOVEL SEMICONDUCTOR AND OPTOELECTRONIC DEVICES'
[patent_app_type] => utility
[patent_app_number] => 13/422049
[patent_app_country] => US
[patent_app_date] => 2012-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 148
[patent_figures_cnt] => 148
[patent_no_of_words] => 23561
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13422049
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/422049 | Method for fabricating novel semiconductor and optoelectronic devices | Mar 15, 2012 | Issued |