Search

Benjamin E. Lanier

Examiner (ID: 11317, Phone: (571)272-3805 , Office: P/2437 )

Most Active Art Unit
2437
Art Unit(s)
2437, 2132, 2432
Total Applications
1337
Issued Applications
871
Pending Applications
110
Abandoned Applications
371

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6624222 [patent_doc_number] => 20100003835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-07 [patent_title] => 'Low-K Precursors Based on Silicon Cryptands, Crown Ethers and Podands' [patent_app_type] => utility [patent_app_number] => 12/497293 [patent_app_country] => US [patent_app_date] => 2009-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3558 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20100003835.pdf [firstpage_image] =>[orig_patent_app_number] => 12497293 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/497293
Low-K Precursors Based on Silicon Cryptands, Crown Ethers and Podands Jul 1, 2009 Abandoned
Array ( [id] => 6512038 [patent_doc_number] => 20100261299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'PACKAGING PROCESS OF LIGHT EMITTING DIODE' [patent_app_type] => utility [patent_app_number] => 12/496644 [patent_app_country] => US [patent_app_date] => 2009-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2678 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20100261299.pdf [firstpage_image] =>[orig_patent_app_number] => 12496644 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/496644
Packaging process of light emitting diode Jul 1, 2009 Issued
Array ( [id] => 4031 [patent_doc_number] => 07816181 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-10-19 [patent_title] => 'Method of under-filling semiconductor die in a die stack and semiconductor device formed thereby' [patent_app_type] => utility [patent_app_number] => 12/494803 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 5172 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/816/07816181.pdf [firstpage_image] =>[orig_patent_app_number] => 12494803 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/494803
Method of under-filling semiconductor die in a die stack and semiconductor device formed thereby Jun 29, 2009 Issued
Array ( [id] => 4528676 [patent_doc_number] => 07923321 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-12 [patent_title] => 'Method for gap filling in a gate last process' [patent_app_type] => utility [patent_app_number] => 12/487894 [patent_app_country] => US [patent_app_date] => 2009-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5232 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/923/07923321.pdf [firstpage_image] =>[orig_patent_app_number] => 12487894 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/487894
Method for gap filling in a gate last process Jun 18, 2009 Issued
Array ( [id] => 4564581 [patent_doc_number] => 07846807 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Method for forming memristor material and electrode structure with memristance' [patent_app_type] => utility [patent_app_number] => 12/486403 [patent_app_country] => US [patent_app_date] => 2009-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 3987 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/846/07846807.pdf [firstpage_image] =>[orig_patent_app_number] => 12486403 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/486403
Method for forming memristor material and electrode structure with memristance Jun 16, 2009 Issued
Array ( [id] => 7550053 [patent_doc_number] => 08062384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-22 [patent_title] => 'Systems, methods and apparatuses for magnetic processing of solar modules' [patent_app_type] => utility [patent_app_number] => 12/483499 [patent_app_country] => US [patent_app_date] => 2009-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 7170 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/062/08062384.pdf [firstpage_image] =>[orig_patent_app_number] => 12483499 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/483499
Systems, methods and apparatuses for magnetic processing of solar modules Jun 11, 2009 Issued
Array ( [id] => 7977399 [patent_doc_number] => 08071446 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-06 [patent_title] => 'Manufacturing method of semiconductor device and substrate processing apparatus' [patent_app_type] => utility [patent_app_number] => 12/457493 [patent_app_country] => US [patent_app_date] => 2009-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9609 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/071/08071446.pdf [firstpage_image] =>[orig_patent_app_number] => 12457493 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/457493
Manufacturing method of semiconductor device and substrate processing apparatus Jun 11, 2009 Issued
Array ( [id] => 4464045 [patent_doc_number] => 07935561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-03 [patent_title] => 'Method of forming shielded gate FET with self-aligned features' [patent_app_type] => utility [patent_app_number] => 12/480031 [patent_app_country] => US [patent_app_date] => 2009-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 45 [patent_no_of_words] => 5099 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/935/07935561.pdf [firstpage_image] =>[orig_patent_app_number] => 12480031 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/480031
Method of forming shielded gate FET with self-aligned features Jun 7, 2009 Issued
Array ( [id] => 5401349 [patent_doc_number] => 20090236662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'GUARD RING STRUCTURES FOR HIGH VOLTAGE CMOS/LOW VOLTAGE CMOS TECHNOLOGY USING LDMOS (LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR) DEVICE FABRICATION' [patent_app_type] => utility [patent_app_number] => 12/475661 [patent_app_country] => US [patent_app_date] => 2009-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4123 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20090236662.pdf [firstpage_image] =>[orig_patent_app_number] => 12475661 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/475661
Guard ring structures for high voltage CMOS/low voltage CMOS technology using LDMOS (lateral double-diffused metal oxide semiconductor) device fabrication May 31, 2009 Issued
Array ( [id] => 7977447 [patent_doc_number] => 08071470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-06 [patent_title] => 'Wafer level package using stud bump coated with solder' [patent_app_type] => utility [patent_app_number] => 12/475362 [patent_app_country] => US [patent_app_date] => 2009-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 3603 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/071/08071470.pdf [firstpage_image] =>[orig_patent_app_number] => 12475362 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/475362
Wafer level package using stud bump coated with solder May 28, 2009 Issued
Array ( [id] => 6375851 [patent_doc_number] => 20100301446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'IN-LINE STACKING OF TRANSISTORS FOR SOFT ERROR RATE HARDENING' [patent_app_type] => utility [patent_app_number] => 12/473409 [patent_app_country] => US [patent_app_date] => 2009-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2130 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0301/20100301446.pdf [firstpage_image] =>[orig_patent_app_number] => 12473409 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/473409
In-line stacking of transistors for soft error rate hardening May 27, 2009 Issued
Array ( [id] => 6106005 [patent_doc_number] => 20110186906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-04 [patent_title] => 'METHODS AND APPARATUS FOR ANTIMONIDE-BASED BACKWARD DIODE MILLIMETER-WAVE DETECTORS' [patent_app_type] => utility [patent_app_number] => 12/993974 [patent_app_country] => US [patent_app_date] => 2009-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4027 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20110186906.pdf [firstpage_image] =>[orig_patent_app_number] => 12993974 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/993974
Methods and apparatus for antimonide-based backward diode millimeter-wave detectors May 26, 2009 Issued
Array ( [id] => 7500690 [patent_doc_number] => 20110263073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'Physical Vapour Deposition Processes' [patent_app_type] => utility [patent_app_number] => 12/994849 [patent_app_country] => US [patent_app_date] => 2009-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11881 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20110263073.pdf [firstpage_image] =>[orig_patent_app_number] => 12994849 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/994849
Physical Vapour Deposition Processes May 24, 2009 Abandoned
Array ( [id] => 5303613 [patent_doc_number] => 20090298265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'Method of Manufacturing III Nitride Crystal, III Nitride Crystal Substrate, and Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 12/470493 [patent_app_country] => US [patent_app_date] => 2009-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7963 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0298/20090298265.pdf [firstpage_image] =>[orig_patent_app_number] => 12470493 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/470493
Method of manufacturing III nitride crystal, III nitride crystal substrate, and semiconductor device May 21, 2009 Issued
Array ( [id] => 4485742 [patent_doc_number] => 07883983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/467519 [patent_app_country] => US [patent_app_date] => 2009-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 45 [patent_no_of_words] => 12517 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/883/07883983.pdf [firstpage_image] =>[orig_patent_app_number] => 12467519 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/467519
Semiconductor device and method of manufacturing the same May 17, 2009 Issued
Array ( [id] => 5473742 [patent_doc_number] => 20090246908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'ROLL-TO-ROLL PROCESSING METHOD AND TOOLS FOR ELECTROLESS DEPOSITION OF THIN LAYERS' [patent_app_type] => utility [patent_app_number] => 12/464673 [patent_app_country] => US [patent_app_date] => 2009-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6867 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20090246908.pdf [firstpage_image] =>[orig_patent_app_number] => 12464673 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/464673
Roll-to-roll processing method and tools for electroless deposition of thin layers May 11, 2009 Issued
Array ( [id] => 5549814 [patent_doc_number] => 20090283800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-19 [patent_title] => 'PHOTOELECTROCHEMICAL ETCHING OF P-TYPE SEMICONDUCTOR HETEROSTRUCTURES' [patent_app_type] => utility [patent_app_number] => 12/464723 [patent_app_country] => US [patent_app_date] => 2009-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6941 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20090283800.pdf [firstpage_image] =>[orig_patent_app_number] => 12464723 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/464723
Photoelectrochemical etching of P-type semiconductor heterostructures May 11, 2009 Issued
Array ( [id] => 9020903 [patent_doc_number] => 08530889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-10 [patent_title] => 'Carbon nanotube composite, organic semiconductor composite, and field-effect transistor' [patent_app_type] => utility [patent_app_number] => 12/992483 [patent_app_country] => US [patent_app_date] => 2009-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 15029 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12992483 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/992483
Carbon nanotube composite, organic semiconductor composite, and field-effect transistor May 10, 2009 Issued
Array ( [id] => 7654750 [patent_doc_number] => 20110304019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-15 [patent_title] => 'METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICES OBTAINED THEREBY' [patent_app_type] => utility [patent_app_number] => 12/994113 [patent_app_country] => US [patent_app_date] => 2009-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 3723 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0304/20110304019.pdf [firstpage_image] =>[orig_patent_app_number] => 12994113 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/994113
Method of manufacturing a bipolar transistor semiconductor device and semiconductor devices obtained thereby May 10, 2009 Issued
Array ( [id] => 4487124 [patent_doc_number] => 07902558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-08 [patent_title] => 'Substrate of liquid crystal device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/453256 [patent_app_country] => US [patent_app_date] => 2009-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 4 [patent_no_of_words] => 4865 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/902/07902558.pdf [firstpage_image] =>[orig_patent_app_number] => 12453256 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/453256
Substrate of liquid crystal device and method for manufacturing the same May 4, 2009 Issued
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