
Benjamin E. Lanier
Examiner (ID: 11317, Phone: (571)272-3805 , Office: P/2437 )
| Most Active Art Unit | 2437 |
| Art Unit(s) | 2437, 2132, 2432 |
| Total Applications | 1337 |
| Issued Applications | 871 |
| Pending Applications | 110 |
| Abandoned Applications | 371 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4800470
[patent_doc_number] => 20080012057
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-17
[patent_title] => 'Semiconductor Device Using Fuse/Anti-Fuse System and Method of Manufacturing the Same'
[patent_app_type] => utility
[patent_app_number] => 11/859388
[patent_app_country] => US
[patent_app_date] => 2007-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 8216
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[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0012/20080012057.pdf
[firstpage_image] =>[orig_patent_app_number] => 11859388
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/859388 | Semiconductor device using fuse/anti-fuse system | Sep 20, 2007 | Issued |
Array
(
[id] => 177830
[patent_doc_number] => 07655538
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-02-02
[patent_title] => 'MEMS device and interposer and method for integrating MEMS device and interposer'
[patent_app_type] => utility
[patent_app_number] => 11/857720
[patent_app_country] => US
[patent_app_date] => 2007-09-19
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/655/07655538.pdf
[firstpage_image] =>[orig_patent_app_number] => 11857720
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/857720 | MEMS device and interposer and method for integrating MEMS device and interposer | Sep 18, 2007 | Issued |
Array
(
[id] => 4571592
[patent_doc_number] => 07829454
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-09
[patent_title] => 'Method for integrating selective ruthenium deposition into manufacturing of a semiconductior device'
[patent_app_type] => utility
[patent_app_number] => 11/853393
[patent_app_country] => US
[patent_app_date] => 2007-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/07/829/07829454.pdf
[firstpage_image] =>[orig_patent_app_number] => 11853393
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/853393 | Method for integrating selective ruthenium deposition into manufacturing of a semiconductior device | Sep 10, 2007 | Issued |
Array
(
[id] => 4733872
[patent_doc_number] => 20080050851
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-28
[patent_title] => 'Method for Manufacturing Display Device'
[patent_app_type] => utility
[patent_app_number] => 11/840043
[patent_app_country] => US
[patent_app_date] => 2007-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 41
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[patent_no_of_words] => 42968
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[pdf_file] => publications/A1/0050/20080050851.pdf
[firstpage_image] =>[orig_patent_app_number] => 11840043
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/840043 | Method for manufacturing display device | Aug 15, 2007 | Issued |
Array
(
[id] => 359599
[patent_doc_number] => 07485478
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-02-03
[patent_title] => 'Light emitting device and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/890494
[patent_app_country] => US
[patent_app_date] => 2007-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
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[pdf_file] => patents/07/485/07485478.pdf
[firstpage_image] =>[orig_patent_app_number] => 11890494
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/890494 | Light emitting device and method of manufacturing the same | Aug 6, 2007 | Issued |
Array
(
[id] => 5288081
[patent_doc_number] => 20090020811
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-01-22
[patent_title] => 'GUARD RING STRUCTURES FOR HIGH VOLTAGE CMOS/LOW VOLTAGE CMOS TECHNOLOGY USING LDMOS (LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR) DEVICE FABRICATION'
[patent_app_type] => utility
[patent_app_number] => 11/778414
[patent_app_country] => US
[patent_app_date] => 2007-07-16
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0020/20090020811.pdf
[firstpage_image] =>[orig_patent_app_number] => 11778414
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/778414 | Guard ring structures for high voltage CMOS/low voltage CMOS technology using LDMOS (lateral double-diffused metal oxide semiconductor) device fabrication | Jul 15, 2007 | Issued |
Array
(
[id] => 5225151
[patent_doc_number] => 20070254417
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-01
[patent_title] => 'METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING A CAPACITOR'
[patent_app_type] => utility
[patent_app_number] => 11/777294
[patent_app_country] => US
[patent_app_date] => 2007-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6333
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[pdf_file] => publications/A1/0254/20070254417.pdf
[firstpage_image] =>[orig_patent_app_number] => 11777294
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/777294 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING A CAPACITOR | Jul 12, 2007 | Abandoned |
Array
(
[id] => 169510
[patent_doc_number] => 07662239
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-02-16
[patent_title] => 'Method of producing group 3 nitride substrate wafers and group 3 nitride substrate wafers'
[patent_app_type] => utility
[patent_app_number] => 11/822903
[patent_app_country] => US
[patent_app_date] => 2007-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 8441
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[pdf_file] => patents/07/662/07662239.pdf
[firstpage_image] =>[orig_patent_app_number] => 11822903
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/822903 | Method of producing group 3 nitride substrate wafers and group 3 nitride substrate wafers | Jul 10, 2007 | Issued |
Array
(
[id] => 345041
[patent_doc_number] => 07498228
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-03-03
[patent_title] => 'Method for fabricating SONOS a memory'
[patent_app_type] => utility
[patent_app_number] => 11/775223
[patent_app_country] => US
[patent_app_date] => 2007-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[pdf_file] => patents/07/498/07498228.pdf
[firstpage_image] =>[orig_patent_app_number] => 11775223
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/775223 | Method for fabricating SONOS a memory | Jul 8, 2007 | Issued |
Array
(
[id] => 330477
[patent_doc_number] => 07510973
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-03-31
[patent_title] => 'Method for forming fine pattern in semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/819854
[patent_app_country] => US
[patent_app_date] => 2007-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[firstpage_image] =>[orig_patent_app_number] => 11819854
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/819854 | Method for forming fine pattern in semiconductor device | Jun 28, 2007 | Issued |
Array
(
[id] => 4932933
[patent_doc_number] => 20080003708
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-03
[patent_title] => 'Method of processing sapphire substrate'
[patent_app_type] => utility
[patent_app_number] => 11/819673
[patent_app_country] => US
[patent_app_date] => 2007-06-28
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[firstpage_image] =>[orig_patent_app_number] => 11819673
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/819673 | Method of processing sapphire substrate | Jun 27, 2007 | Abandoned |
Array
(
[id] => 4933060
[patent_doc_number] => 20080003835
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[patent_kind] => A1
[patent_issue_date] => 2008-01-03
[patent_title] => 'Method for Fabricating Semiconductor Device'
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[firstpage_image] =>[orig_patent_app_number] => 11770193
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/770193 | Method for fabricating silicide layers for semiconductor device | Jun 27, 2007 | Issued |
Array
(
[id] => 233135
[patent_doc_number] => 07598562
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[patent_title] => 'Semiconductor device and method of manufacturing the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/769423 | Semiconductor device and method of manufacturing the same | Jun 26, 2007 | Issued |
Array
(
[id] => 4483341
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[patent_title] => 'Method of constructing a stacked-die semiconductor structure'
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Array
(
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Array
(
[id] => 101168
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[patent_issue_date] => 2010-06-01
[patent_title] => 'Inclusion of nitrogen at the silicon dioxide-silicon carbide interface for passivation of interface defects'
[patent_app_type] => utility
[patent_app_number] => 11/811396
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Array
(
[id] => 259982
[patent_doc_number] => 07572707
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[patent_title] => 'Method of manufacturing NPN device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/754234 | Method of manufacturing NPN device | May 24, 2007 | Issued |
Array
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/797783 | Method for manufacturing substrate of liquid crystal device | May 7, 2007 | Issued |
Array
(
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[firstpage_image] =>[orig_patent_app_number] => 11744743
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/744743 | Extended redistribution layers bumped wafer | May 3, 2007 | Issued |