
Benjamin E. Lanier
Examiner (ID: 11317, Phone: (571)272-3805 , Office: P/2437 )
| Most Active Art Unit | 2437 |
| Art Unit(s) | 2437, 2132, 2432 |
| Total Applications | 1337 |
| Issued Applications | 871 |
| Pending Applications | 110 |
| Abandoned Applications | 371 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5129969
[patent_doc_number] => 20070206366
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-06
[patent_title] => 'Method for embedding a component in a base'
[patent_app_type] => utility
[patent_app_number] => 11/797609
[patent_app_country] => US
[patent_app_date] => 2007-05-04
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0206/20070206366.pdf
[firstpage_image] =>[orig_patent_app_number] => 11797609
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/797609 | Method for embedding a component in a base | May 3, 2007 | Issued |
Array
(
[id] => 5163064
[patent_doc_number] => 20070284645
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[patent_kind] => A1
[patent_issue_date] => 2007-12-13
[patent_title] => 'Non-volatile memory devices having a multi-layered charge storage layer and methods of forming the same'
[patent_app_type] => utility
[patent_app_number] => 11/799685
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/799685 | Methods of forming non-volatile memory devices having a multi-layered charge storage layer | May 1, 2007 | Issued |
Array
(
[id] => 5005080
[patent_doc_number] => 20070202650
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[patent_issue_date] => 2007-08-30
[patent_title] => 'Low voltage power MOSFET device and process for its manufacture'
[patent_app_type] => utility
[patent_app_number] => 11/796303
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/796303 | Low voltage power MOSFET device and process for its manufacture | Apr 26, 2007 | Issued |
Array
(
[id] => 7595255
[patent_doc_number] => 07626206
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[patent_kind] => B2
[patent_issue_date] => 2009-12-01
[patent_title] => 'Liquid crystal display device and fabricating method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/790068
[patent_app_country] => US
[patent_app_date] => 2007-04-23
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 11790068
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/790068 | Liquid crystal display device and fabricating method thereof | Apr 22, 2007 | Issued |
Array
(
[id] => 7523397
[patent_doc_number] => 08026556
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-09-27
[patent_title] => 'Adjustible resistor for use in a resistive divider circuit and method for manufacturing'
[patent_app_type] => utility
[patent_app_number] => 12/297281
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[patent_app_date] => 2007-04-19
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[pdf_file] => patents/08/026/08026556.pdf
[firstpage_image] =>[orig_patent_app_number] => 12297281
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/297281 | Adjustible resistor for use in a resistive divider circuit and method for manufacturing | Apr 18, 2007 | Issued |
Array
(
[id] => 5101397
[patent_doc_number] => 20070184659
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[patent_issue_date] => 2007-08-09
[patent_title] => 'Method for Cleaning a Semiconductor Wafer'
[patent_app_type] => utility
[patent_app_number] => 11/697883
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[firstpage_image] =>[orig_patent_app_number] => 11697883
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/697883 | Method for cleaning a semiconductor wafer | Apr 8, 2007 | Issued |
Array
(
[id] => 5173962
[patent_doc_number] => 20070175019
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[patent_kind] => A1
[patent_issue_date] => 2007-08-02
[patent_title] => 'ELECTRICAL COMPONENT, METHOD FOR THE MANUFACTURE THEREOF AND EMPLOYMENT THEREOF'
[patent_app_type] => utility
[patent_app_number] => 11/697844
[patent_app_country] => US
[patent_app_date] => 2007-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => publications/A1/0175/20070175019.pdf
[firstpage_image] =>[orig_patent_app_number] => 11697844
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/697844 | Method for the manufacture of electrical component | Apr 8, 2007 | Issued |
Array
(
[id] => 4682374
[patent_doc_number] => 20080248600
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-09
[patent_title] => 'METHOD AND DEVICE FOR WAFER BACKSIDE ALIGNMENT OVERLAY ACCURACY'
[patent_app_type] => utility
[patent_app_number] => 11/697543
[patent_app_country] => US
[patent_app_date] => 2007-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => publications/A1/0248/20080248600.pdf
[firstpage_image] =>[orig_patent_app_number] => 11697543
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/697543 | Method and device for wafer backside alignment overlay accuracy | Apr 5, 2007 | Issued |
Array
(
[id] => 7691968
[patent_doc_number] => 20070232065
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[patent_kind] => A1
[patent_issue_date] => 2007-10-04
[patent_title] => 'Composition Control For Photovoltaic Thin Film Manufacturing'
[patent_app_type] => utility
[patent_app_number] => 11/696643
[patent_app_country] => US
[patent_app_date] => 2007-04-04
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[firstpage_image] =>[orig_patent_app_number] => 11696643
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/696643 | Composition control for photovoltaic thin film manufacturing | Apr 3, 2007 | Issued |
Array
(
[id] => 5122294
[patent_doc_number] => 20070234563
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-11
[patent_title] => 'METHOD OF FORMING SOLDER CONNECTION PORTIONS, METHOD OF FORMING WIRING SUBSTRATE AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/696473
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 11696473
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/696473 | Method of forming solder connection portions, method of forming wiring substrate and method of producing semiconductor device | Apr 3, 2007 | Issued |
Array
(
[id] => 224825
[patent_doc_number] => 07605008
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[patent_issue_date] => 2009-10-20
[patent_title] => 'Plasma ignition and complete faraday shielding of capacitive coupling for an inductively-coupled plasma'
[patent_app_type] => utility
[patent_app_number] => 11/695553
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/695553 | Plasma ignition and complete faraday shielding of capacitive coupling for an inductively-coupled plasma | Apr 1, 2007 | Issued |
Array
(
[id] => 4719591
[patent_doc_number] => 20080242114
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[patent_title] => 'THERMAL ANNEAL METHOD FOR A HIGH-K DIELECTRIC'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/695324 | THERMAL ANNEAL METHOD FOR A HIGH-K DIELECTRIC | Apr 1, 2007 | Abandoned |
Array
(
[id] => 4719547
[patent_doc_number] => 20080242070
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[patent_issue_date] => 2008-10-02
[patent_title] => 'INTEGRATION SCHEMES FOR FABRICATING POLYSILICON GATE MOSFET AND HIGH-K DIELECTRIC METAL GATE MOSFET'
[patent_app_type] => utility
[patent_app_number] => 11/694104
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[firstpage_image] =>[orig_patent_app_number] => 11694104
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/694104 | Integration schemes for fabricating polysilicon gate MOSFET and high-K dielectric metal gate MOSFET | Mar 29, 2007 | Issued |
Array
(
[id] => 4719506
[patent_doc_number] => 20080242029
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[patent_title] => 'METHOD AND STRUCTURE FOR MAKING A TOP-SIDE CONTACT TO A SUBSTRATE'
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Array
(
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[patent_title] => 'Strained Si on multiple materials for bulk or SOI substrates'
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Array
(
[id] => 4719475
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[patent_title] => 'METHOD FOR FABRICATING A LOW COST INTEGRATED CIRCUIT (IC) PACKAGE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/694744 | Method for fabricating a low cost integrated circuit (IC) package | Mar 29, 2007 | Issued |
Array
(
[id] => 602428
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[patent_title] => 'Method of forming a dual damascene structure utilizing a developable anti-reflective coating'
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[patent_app_number] => 11/694623
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Array
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Array
(
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[patent_title] => 'METHOD AND STRUCTURE FOR ULTRA NARROW CRACK STOP FOR MULTILEVEL SEMICONDUCTOR DEVICE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/693033 | Method and structure for ultra narrow crack stop for multilevel semiconductor device | Mar 28, 2007 | Issued |
Array
(
[id] => 4740056
[patent_doc_number] => 20080233709
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[patent_issue_date] => 2008-09-25
[patent_title] => 'METHOD FOR REMOVING MATERIAL FROM A SEMICONDUCTOR'
[patent_app_type] => utility
[patent_app_number] => 11/689884
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/689884 | METHOD FOR REMOVING MATERIAL FROM A SEMICONDUCTOR | Mar 21, 2007 | Abandoned |