Search

Benjamin E. Lanier

Examiner (ID: 11317, Phone: (571)272-3805 , Office: P/2437 )

Most Active Art Unit
2437
Art Unit(s)
2437, 2132, 2432
Total Applications
1337
Issued Applications
871
Pending Applications
110
Abandoned Applications
371

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4913104 [patent_doc_number] => 20080093703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'ELECTRICAL FUSE AND METHOD OF MAKING' [patent_app_type] => utility [patent_app_number] => 11/550943 [patent_app_country] => US [patent_app_date] => 2006-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3816 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20080093703.pdf [firstpage_image] =>[orig_patent_app_number] => 11550943 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/550943
Electrical fuse and method of making Oct 18, 2006 Issued
Array ( [id] => 8968491 [patent_doc_number] => 08507302 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-13 [patent_title] => 'Wall structures for a semiconductor wafer' [patent_app_type] => utility [patent_app_number] => 11/548624 [patent_app_country] => US [patent_app_date] => 2006-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 47 [patent_no_of_words] => 5784 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11548624 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/548624
Wall structures for a semiconductor wafer Oct 10, 2006 Issued
Array ( [id] => 5538533 [patent_doc_number] => 20090220338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-03 [patent_title] => 'Fluid Compressor with Aerostatic Bearing, Control System of a Compressor with Aerostatic Bearing and Method of Controlling a Compressor with Aerostatic Bearing' [patent_app_type] => utility [patent_app_number] => 12/089967 [patent_app_country] => US [patent_app_date] => 2006-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2747 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20090220338.pdf [firstpage_image] =>[orig_patent_app_number] => 12089967 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/089967
Fluid Compressor with Aerostatic Bearing, Control System of a Compressor with Aerostatic Bearing and Method of Controlling a Compressor with Aerostatic Bearing Oct 10, 2006 Abandoned
Array ( [id] => 101922 [patent_doc_number] => 07727793 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-01 [patent_title] => 'Physical quantity sensor and manufacturing method therefor' [patent_app_type] => utility [patent_app_number] => 11/543034 [patent_app_country] => US [patent_app_date] => 2006-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 37 [patent_no_of_words] => 14189 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/727/07727793.pdf [firstpage_image] =>[orig_patent_app_number] => 11543034 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/543034
Physical quantity sensor and manufacturing method therefor Oct 4, 2006 Issued
Array ( [id] => 4922050 [patent_doc_number] => 20080070365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Shielded Gate FET with Self-Aligned Features' [patent_app_type] => utility [patent_app_number] => 11/536584 [patent_app_country] => US [patent_app_date] => 2006-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5456 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20080070365.pdf [firstpage_image] =>[orig_patent_app_number] => 11536584 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/536584
Trench gate FET with self-aligned features Sep 27, 2006 Issued
Array ( [id] => 4983014 [patent_doc_number] => 20070087572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'Method and apparatus for the improvement of material/voltage contrast' [patent_app_type] => utility [patent_app_number] => 11/527434 [patent_app_country] => US [patent_app_date] => 2006-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10292 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20070087572.pdf [firstpage_image] =>[orig_patent_app_number] => 11527434 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/527434
Method and apparatus for the improvement of material/voltage contrast Sep 25, 2006 Abandoned
Array ( [id] => 5168848 [patent_doc_number] => 20070069279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Semiconductor memory and method of manufacturing same' [patent_app_type] => utility [patent_app_number] => 11/526014 [patent_app_country] => US [patent_app_date] => 2006-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4357 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20070069279.pdf [firstpage_image] =>[orig_patent_app_number] => 11526014 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/526014
Semiconductor memory with sense amplifier Sep 24, 2006 Issued
Array ( [id] => 4826020 [patent_doc_number] => 20080124925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'METHOD FOR IMPROVED FORMATION OF COBALT SILICIDE CONTACTS IN SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 11/534714 [patent_app_country] => US [patent_app_date] => 2006-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1791 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20080124925.pdf [firstpage_image] =>[orig_patent_app_number] => 11534714 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/534714
Method for improved formation of cobalt silicide contacts in semiconductor devices Sep 24, 2006 Issued
Array ( [id] => 5171890 [patent_doc_number] => 20070072323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Method of manufacturing display panel for flexible display device' [patent_app_type] => utility [patent_app_number] => 11/526174 [patent_app_country] => US [patent_app_date] => 2006-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 7626 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20070072323.pdf [firstpage_image] =>[orig_patent_app_number] => 11526174 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/526174
Method of manufacturing display panel for flexible display device Sep 20, 2006 Issued
Array ( [id] => 4825924 [patent_doc_number] => 20080124870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Trench Gate FET with Self-Aligned Features' [patent_app_type] => utility [patent_app_number] => 11/533493 [patent_app_country] => US [patent_app_date] => 2006-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4145 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20080124870.pdf [firstpage_image] =>[orig_patent_app_number] => 11533493 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/533493
Trench Gate FET with Self-Aligned Features Sep 19, 2006 Abandoned
Array ( [id] => 356248 [patent_doc_number] => 07488684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-10 [patent_title] => 'Organic aluminum precursor and method of forming a metal wire using the same' [patent_app_type] => utility [patent_app_number] => 11/523604 [patent_app_country] => US [patent_app_date] => 2006-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5762 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/488/07488684.pdf [firstpage_image] =>[orig_patent_app_number] => 11523604 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/523604
Organic aluminum precursor and method of forming a metal wire using the same Sep 19, 2006 Issued
Array ( [id] => 5193973 [patent_doc_number] => 20070082457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'Method For Filling Of Nanoscale Holes And Trenches And For Planarizing Of A Wafer Surface' [patent_app_type] => utility [patent_app_number] => 11/533323 [patent_app_country] => US [patent_app_date] => 2006-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3904 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20070082457.pdf [firstpage_image] =>[orig_patent_app_number] => 11533323 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/533323
Method for filling of nanoscale holes and trenches and for planarizing of a wafer surface Sep 18, 2006 Issued
Array ( [id] => 363436 [patent_doc_number] => 07482247 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-01-27 [patent_title] => 'Conformal nanolaminate dielectric deposition and etch bag gap fill process' [patent_app_type] => utility [patent_app_number] => 11/524502 [patent_app_country] => US [patent_app_date] => 2006-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 10011 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/482/07482247.pdf [firstpage_image] =>[orig_patent_app_number] => 11524502 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/524502
Conformal nanolaminate dielectric deposition and etch bag gap fill process Sep 18, 2006 Issued
Array ( [id] => 5105884 [patent_doc_number] => 20070064759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-22 [patent_title] => 'Method for manufacturing semiconductor laser device and semiconductor laser device' [patent_app_type] => utility [patent_app_number] => 11/522356 [patent_app_country] => US [patent_app_date] => 2006-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7664 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20070064759.pdf [firstpage_image] =>[orig_patent_app_number] => 11522356 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/522356
Method for manufacturing semiconductor laser device and semiconductor laser device Sep 17, 2006 Issued
Array ( [id] => 576806 [patent_doc_number] => 07456096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-25 [patent_title] => 'Method of manufacturing silicide layer for semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/530724 [patent_app_country] => US [patent_app_date] => 2006-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 33 [patent_no_of_words] => 9984 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/456/07456096.pdf [firstpage_image] =>[orig_patent_app_number] => 11530724 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/530724
Method of manufacturing silicide layer for semiconductor device Sep 10, 2006 Issued
Array ( [id] => 856696 [patent_doc_number] => 07374955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-20 [patent_title] => 'Method of manufacturing silicon wafer' [patent_app_type] => utility [patent_app_number] => 11/518514 [patent_app_country] => US [patent_app_date] => 2006-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2976 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/374/07374955.pdf [firstpage_image] =>[orig_patent_app_number] => 11518514 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/518514
Method of manufacturing silicon wafer Sep 10, 2006 Issued
Array ( [id] => 292232 [patent_doc_number] => 07544521 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-06-09 [patent_title] => 'Negative bias critical dimension trim' [patent_app_type] => utility [patent_app_number] => 11/519384 [patent_app_country] => US [patent_app_date] => 2006-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4086 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/544/07544521.pdf [firstpage_image] =>[orig_patent_app_number] => 11519384 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/519384
Negative bias critical dimension trim Sep 10, 2006 Issued
Array ( [id] => 5602399 [patent_doc_number] => 20060292744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Three dimensional device integration method and integrated device' [patent_app_type] => utility [patent_app_number] => 11/514083 [patent_app_country] => US [patent_app_date] => 2006-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 12955 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0292/20060292744.pdf [firstpage_image] =>[orig_patent_app_number] => 11514083 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/514083
Three dimensional device integration method and integrated device Aug 31, 2006 Abandoned
Array ( [id] => 7703360 [patent_doc_number] => 08089117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-03 [patent_title] => 'Semiconductor structure' [patent_app_type] => utility [patent_app_number] => 12/065901 [patent_app_country] => US [patent_app_date] => 2006-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 11582 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/089/08089117.pdf [firstpage_image] =>[orig_patent_app_number] => 12065901 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/065901
Semiconductor structure Aug 21, 2006 Issued
Array ( [id] => 584990 [patent_doc_number] => 07442603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Self-aligned structure and method for confining a melting point in a resistor random access memory' [patent_app_type] => utility [patent_app_number] => 11/465094 [patent_app_country] => US [patent_app_date] => 2006-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4831 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/442/07442603.pdf [firstpage_image] =>[orig_patent_app_number] => 11465094 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/465094
Self-aligned structure and method for confining a melting point in a resistor random access memory Aug 15, 2006 Issued
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