
Benjamin E. Lanier
Examiner (ID: 11317, Phone: (571)272-3805 , Office: P/2437 )
| Most Active Art Unit | 2437 |
| Art Unit(s) | 2437, 2132, 2432 |
| Total Applications | 1337 |
| Issued Applications | 871 |
| Pending Applications | 110 |
| Abandoned Applications | 371 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5851247
[patent_doc_number] => 20060234438
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-19
[patent_title] => 'Self-aligned contact for silicon-on-insulator devices'
[patent_app_type] => utility
[patent_app_number] => 11/454600
[patent_app_country] => US
[patent_app_date] => 2006-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 3966
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0234/20060234438.pdf
[firstpage_image] =>[orig_patent_app_number] => 11454600
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/454600 | Self-aligned contact for silicon-on-insulator devices | Jun 15, 2006 | Abandoned |
Array
(
[id] => 5659190
[patent_doc_number] => 20060249786
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-09
[patent_title] => 'Alignment of trench for MOS'
[patent_app_type] => utility
[patent_app_number] => 11/408924
[patent_app_country] => US
[patent_app_date] => 2006-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[firstpage_image] =>[orig_patent_app_number] => 11408924
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/408924 | Alignment of trench for MOS | Apr 23, 2006 | Issued |
Array
(
[id] => 5848508
[patent_doc_number] => 20060231830
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-19
[patent_title] => 'DISPLAY DEVICE AND A METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/279930
[patent_app_country] => US
[patent_app_date] => 2006-04-17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/279930 | Display device and a method of manufacturing the same | Apr 16, 2006 | Issued |
Array
(
[id] => 889140
[patent_doc_number] => 07348653
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-03-25
[patent_title] => 'Resistive memory cell, method for forming the same and resistive memory array using the same'
[patent_app_type] => utility
[patent_app_number] => 11/279640
[patent_app_country] => US
[patent_app_date] => 2006-04-13
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 11279640
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/279640 | Resistive memory cell, method for forming the same and resistive memory array using the same | Apr 12, 2006 | Issued |
Array
(
[id] => 872168
[patent_doc_number] => 07361591
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-04-22
[patent_title] => 'Method of fabricating semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/279364
[patent_app_country] => US
[patent_app_date] => 2006-04-11
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[patent_drawing_sheets_cnt] => 16
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[pdf_file] => patents/07/361/07361591.pdf
[firstpage_image] =>[orig_patent_app_number] => 11279364
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/279364 | Method of fabricating semiconductor memory device | Apr 10, 2006 | Issued |
Array
(
[id] => 5677904
[patent_doc_number] => 20060183260
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[patent_kind] => A1
[patent_issue_date] => 2006-08-17
[patent_title] => 'P-type nitride semiconductor and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/395128
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[patent_app_date] => 2006-04-03
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[firstpage_image] =>[orig_patent_app_number] => 11395128
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/395128 | P-type nitride semiconductor and method of manufacturing the same | Apr 2, 2006 | Abandoned |
Array
(
[id] => 5596369
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[patent_kind] => A1
[patent_issue_date] => 2006-07-20
[patent_title] => 'Memory device and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/385217
[patent_app_country] => US
[patent_app_date] => 2006-03-20
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[patent_drawing_sheets_cnt] => 11
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[firstpage_image] =>[orig_patent_app_number] => 11385217
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/385217 | Memory device and method for fabricating the same | Mar 19, 2006 | Issued |
Array
(
[id] => 5869073
[patent_doc_number] => 20060163690
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-27
[patent_title] => 'Semiconductor having thick dielectric regions'
[patent_app_type] => utility
[patent_app_number] => 11/384565
[patent_app_country] => US
[patent_app_date] => 2006-03-20
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[patent_drawing_sheets_cnt] => 9
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[pdf_file] => publications/A1/0163/20060163690.pdf
[firstpage_image] =>[orig_patent_app_number] => 11384565
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/384565 | Semiconductor having thick dielectric regions | Mar 19, 2006 | Issued |
Array
(
[id] => 481189
[patent_doc_number] => 07220324
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-22
[patent_title] => 'Technique for the growth of planar semi-polar gallium nitride'
[patent_app_type] => utility
[patent_app_number] => 11/372914
[patent_app_country] => US
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[pdf_file] => patents/07/220/07220324.pdf
[firstpage_image] =>[orig_patent_app_number] => 11372914
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/372914 | Technique for the growth of planar semi-polar gallium nitride | Mar 9, 2006 | Issued |
Array
(
[id] => 345035
[patent_doc_number] => 07498222
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-03-03
[patent_title] => 'Enhanced etching of a high dielectric constant layer'
[patent_app_type] => utility
[patent_app_number] => 11/371024
[patent_app_country] => US
[patent_app_date] => 2006-03-09
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[firstpage_image] =>[orig_patent_app_number] => 11371024
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/371024 | Enhanced etching of a high dielectric constant layer | Mar 8, 2006 | Issued |
Array
(
[id] => 5110458
[patent_doc_number] => 20070194373
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[patent_issue_date] => 2007-08-23
[patent_title] => 'CMOS STRUCTURE AND METHOD INCLUDING MULTIPLE CRYSTALLOGRAPHIC PLANES'
[patent_app_type] => utility
[patent_app_number] => 11/276274
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/276274 | CMOS structure and method including multiple crystallographic planes | Feb 21, 2006 | Issued |
Array
(
[id] => 5645540
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[patent_title] => 'Particle-removing apparatus for a semiconductor device manufacturing apparatus and method of removing particles'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/354506 | Particle-removing apparatus for a semiconductor device manufacturing apparatus and method of removing particles | Feb 14, 2006 | Abandoned |
Array
(
[id] => 904265
[patent_doc_number] => 07335927
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[patent_issue_date] => 2008-02-26
[patent_title] => 'Lateral silicided diodes'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/275794 | Lateral silicided diodes | Jan 29, 2006 | Issued |
Array
(
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Array
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Array
(
[id] => 345047
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Array
(
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/301063 | In situ deposition of a low K dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application | Dec 11, 2005 | Issued |
Array
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[firstpage_image] =>[orig_patent_app_number] => 11291508
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/291508 | Semiconductor processing methods | Nov 30, 2005 | Issued |