Search

Benjamin E. Lanier

Examiner (ID: 11317, Phone: (571)272-3805 , Office: P/2437 )

Most Active Art Unit
2437
Art Unit(s)
2437, 2132, 2432
Total Applications
1337
Issued Applications
871
Pending Applications
110
Abandoned Applications
371

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 923268 [patent_doc_number] => 07319240 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-15 [patent_title] => 'Array substrate with reduced pixel defect, method of manufacturing the same and liquid crystal display panel having the same' [patent_app_type] => utility [patent_app_number] => 11/220933 [patent_app_country] => US [patent_app_date] => 2005-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5124 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/319/07319240.pdf [firstpage_image] =>[orig_patent_app_number] => 11220933 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/220933
Array substrate with reduced pixel defect, method of manufacturing the same and liquid crystal display panel having the same Sep 5, 2005 Issued
Array ( [id] => 5823794 [patent_doc_number] => 20060060976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Integrated circuit comprising copper lines and process for forming copper lines' [patent_app_type] => utility [patent_app_number] => 11/220353 [patent_app_country] => US [patent_app_date] => 2005-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1609 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20060060976.pdf [firstpage_image] =>[orig_patent_app_number] => 11220353 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/220353
Process for forming integrated circuit comprising copper lines Sep 5, 2005 Issued
Array ( [id] => 5148972 [patent_doc_number] => 20070049032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Protective coating for planarization' [patent_app_type] => utility [patent_app_number] => 11/219604 [patent_app_country] => US [patent_app_date] => 2005-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 15868 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20070049032.pdf [firstpage_image] =>[orig_patent_app_number] => 11219604 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/219604
Protective coating for planarization Aug 31, 2005 Issued
Array ( [id] => 476355 [patent_doc_number] => 07227181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-05 [patent_title] => 'Organic light emitting device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/216163 [patent_app_country] => US [patent_app_date] => 2005-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 4467 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/227/07227181.pdf [firstpage_image] =>[orig_patent_app_number] => 11216163 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/216163
Organic light emitting device and method of fabricating the same Aug 31, 2005 Issued
Array ( [id] => 394336 [patent_doc_number] => 07298035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-20 [patent_title] => 'Semiconductor device and a method of assembling a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/216144 [patent_app_country] => US [patent_app_date] => 2005-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 40 [patent_no_of_words] => 6353 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/298/07298035.pdf [firstpage_image] =>[orig_patent_app_number] => 11216144 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/216144
Semiconductor device and a method of assembling a semiconductor device Aug 31, 2005 Issued
Array ( [id] => 5903472 [patent_doc_number] => 20060046397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Method for manufacturing trench MOSFET' [patent_app_type] => utility [patent_app_number] => 11/202733 [patent_app_country] => US [patent_app_date] => 2005-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2831 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20060046397.pdf [firstpage_image] =>[orig_patent_app_number] => 11202733 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/202733
Method for manufacturing trench MOSFET Aug 11, 2005 Issued
Array ( [id] => 896165 [patent_doc_number] => 07342251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-11 [patent_title] => 'Method of manufacturing an electro-optical device' [patent_app_type] => utility [patent_app_number] => 11/202143 [patent_app_country] => US [patent_app_date] => 2005-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 36 [patent_no_of_words] => 15589 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/342/07342251.pdf [firstpage_image] =>[orig_patent_app_number] => 11202143 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/202143
Method of manufacturing an electro-optical device Aug 11, 2005 Issued
Array ( [id] => 448515 [patent_doc_number] => 07250335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-31 [patent_title] => 'Methods of fabricating integrated circuit devices including self-aligned contacts with increased alignment margin' [patent_app_type] => utility [patent_app_number] => 11/201803 [patent_app_country] => US [patent_app_date] => 2005-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 34 [patent_no_of_words] => 3954 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/250/07250335.pdf [firstpage_image] =>[orig_patent_app_number] => 11201803 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/201803
Methods of fabricating integrated circuit devices including self-aligned contacts with increased alignment margin Aug 10, 2005 Issued
Array ( [id] => 833427 [patent_doc_number] => 07396716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-08 [patent_title] => 'Method to obtain fully silicided poly gate' [patent_app_type] => utility [patent_app_number] => 11/201924 [patent_app_country] => US [patent_app_date] => 2005-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5849 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/396/07396716.pdf [firstpage_image] =>[orig_patent_app_number] => 11201924 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/201924
Method to obtain fully silicided poly gate Aug 10, 2005 Issued
Array ( [id] => 7605453 [patent_doc_number] => 07115476 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-03 [patent_title] => 'Semiconductor manufacturing method and semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/201264 [patent_app_country] => US [patent_app_date] => 2005-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 68 [patent_no_of_words] => 14141 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/115/07115476.pdf [firstpage_image] =>[orig_patent_app_number] => 11201264 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/201264
Semiconductor manufacturing method and semiconductor device Aug 10, 2005 Issued
Array ( [id] => 521718 [patent_doc_number] => 07186631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'Method for manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/201843 [patent_app_country] => US [patent_app_date] => 2005-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2777 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/186/07186631.pdf [firstpage_image] =>[orig_patent_app_number] => 11201843 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/201843
Method for manufacturing a semiconductor device Aug 10, 2005 Issued
Array ( [id] => 5154458 [patent_doc_number] => 20070037341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'Method and structure for shallow trench isolation during integrated circuit device manufacture' [patent_app_type] => utility [patent_app_number] => 11/200694 [patent_app_country] => US [patent_app_date] => 2005-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4188 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20070037341.pdf [firstpage_image] =>[orig_patent_app_number] => 11200694 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/200694
Method and structure for shallow trench isolation during integrated circuit device manufacture Aug 9, 2005 Issued
Array ( [id] => 5828359 [patent_doc_number] => 20060063376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Method of fabricating dual damascene interconnections of microelectronic device using diffusion barrier layer against base material' [patent_app_type] => utility [patent_app_number] => 11/195404 [patent_app_country] => US [patent_app_date] => 2005-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8591 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20060063376.pdf [firstpage_image] =>[orig_patent_app_number] => 11195404 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/195404
Method of fabricating dual damascene interconnections of microelectronic device using diffusion barrier layer against base material Aug 1, 2005 Issued
Array ( [id] => 582220 [patent_doc_number] => 07449410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-11 [patent_title] => 'Methods of forming CoSi2, methods of forming field effect transistors, and methods of forming conductive contacts' [patent_app_type] => utility [patent_app_number] => 11/195174 [patent_app_country] => US [patent_app_date] => 2005-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 5455 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/449/07449410.pdf [firstpage_image] =>[orig_patent_app_number] => 11195174 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/195174
Methods of forming CoSi2, methods of forming field effect transistors, and methods of forming conductive contacts Aug 1, 2005 Issued
Array ( [id] => 5652682 [patent_doc_number] => 20060138417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Liquid crystal display device and fabricating method thereof' [patent_app_type] => utility [patent_app_number] => 11/168313 [patent_app_country] => US [patent_app_date] => 2005-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 4527 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20060138417.pdf [firstpage_image] =>[orig_patent_app_number] => 11168313 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/168313
Liquid crystal display device and fabricating method thereof Jun 28, 2005 Issued
Array ( [id] => 267076 [patent_doc_number] => 07566601 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-28 [patent_title] => 'Method of making a one transistor SOI non-volatile random access memory cell' [patent_app_type] => utility [patent_app_number] => 11/158744 [patent_app_country] => US [patent_app_date] => 2005-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 28 [patent_no_of_words] => 9099 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/566/07566601.pdf [firstpage_image] =>[orig_patent_app_number] => 11158744 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/158744
Method of making a one transistor SOI non-volatile random access memory cell Jun 21, 2005 Issued
Array ( [id] => 393911 [patent_doc_number] => 07297604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-20 [patent_title] => 'Semiconductor device having dual isolation structure and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/154385 [patent_app_country] => US [patent_app_date] => 2005-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5439 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/297/07297604.pdf [firstpage_image] =>[orig_patent_app_number] => 11154385 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/154385
Semiconductor device having dual isolation structure and method of fabricating the same Jun 15, 2005 Issued
Array ( [id] => 754343 [patent_doc_number] => 07018905 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-28 [patent_title] => 'Method of forming isolation film in semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/150033 [patent_app_country] => US [patent_app_date] => 2005-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2071 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/018/07018905.pdf [firstpage_image] =>[orig_patent_app_number] => 11150033 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/150033
Method of forming isolation film in semiconductor device Jun 9, 2005 Issued
Array ( [id] => 377408 [patent_doc_number] => 07312509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Digital temperature sensing device using temperature depending characteristic of contact resistance' [patent_app_type] => utility [patent_app_number] => 11/146043 [patent_app_country] => US [patent_app_date] => 2005-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 3900 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/312/07312509.pdf [firstpage_image] =>[orig_patent_app_number] => 11146043 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/146043
Digital temperature sensing device using temperature depending characteristic of contact resistance Jun 6, 2005 Issued
Array ( [id] => 5245202 [patent_doc_number] => 20070241436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'Adhesive Bonding Sheet, Semiconductor Device using the Same, and Method for Manufacturing such Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 11/596923 [patent_app_country] => US [patent_app_date] => 2005-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10892 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20070241436.pdf [firstpage_image] =>[orig_patent_app_number] => 11596923 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/596923
Adhesive bonding sheet, semiconductor device using the same, and method for manufacturing such semiconductor device May 16, 2005 Issued
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