
Benjamin E. Lanier
Examiner (ID: 11317, Phone: (571)272-3805 , Office: P/2437 )
| Most Active Art Unit | 2437 |
| Art Unit(s) | 2437, 2132, 2432 |
| Total Applications | 1337 |
| Issued Applications | 871 |
| Pending Applications | 110 |
| Abandoned Applications | 371 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 923268
[patent_doc_number] => 07319240
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[patent_issue_date] => 2008-01-15
[patent_title] => 'Array substrate with reduced pixel defect, method of manufacturing the same and liquid crystal display panel having the same'
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Array
(
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[patent_issue_date] => 2006-03-23
[patent_title] => 'Integrated circuit comprising copper lines and process for forming copper lines'
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Array
(
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Array
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Array
(
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Array
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Array
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Array
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[patent_title] => 'Methods of fabricating integrated circuit devices including self-aligned contacts with increased alignment margin'
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Array
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[patent_title] => 'Method to obtain fully silicided poly gate'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/201924 | Method to obtain fully silicided poly gate | Aug 10, 2005 | Issued |
Array
(
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Array
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Array
(
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Array
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Array
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Array
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