Search

Benjamin E. Lanier

Examiner (ID: 11317, Phone: (571)272-3805 , Office: P/2437 )

Most Active Art Unit
2437
Art Unit(s)
2437, 2132, 2432
Total Applications
1337
Issued Applications
871
Pending Applications
110
Abandoned Applications
371

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6996836 [patent_doc_number] => 20050136614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Methods of forming shallow trench isolation' [patent_app_type] => utility [patent_app_number] => 11/021803 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 922 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20050136614.pdf [firstpage_image] =>[orig_patent_app_number] => 11021803 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/021803
Methods of forming shallow trench isolation Dec 22, 2004 Issued
Array ( [id] => 769023 [patent_doc_number] => 07005332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-28 [patent_title] => 'Fabrication method of thin film transistor' [patent_app_type] => utility [patent_app_number] => 11/019074 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 1711 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/005/07005332.pdf [firstpage_image] =>[orig_patent_app_number] => 11019074 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/019074
Fabrication method of thin film transistor Dec 20, 2004 Issued
Array ( [id] => 6903379 [patent_doc_number] => 20050098774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'Method of forming multiple gate insulators on a strained semiconductor heterostructure' [patent_app_type] => utility [patent_app_number] => 11/015266 [patent_app_country] => US [patent_app_date] => 2004-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2637 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20050098774.pdf [firstpage_image] =>[orig_patent_app_number] => 11015266 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/015266
Method of forming multiple gate insulators on a strained semiconductor heterostructure Dec 16, 2004 Issued
Array ( [id] => 6978104 [patent_doc_number] => 20050287822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Method of forming polysilicon layer in semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/016413 [patent_app_country] => US [patent_app_date] => 2004-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1637 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20050287822.pdf [firstpage_image] =>[orig_patent_app_number] => 11016413 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/016413
Method of forming polysilicon layer in semiconductor device Dec 16, 2004 Issued
Array ( [id] => 751898 [patent_doc_number] => 07023069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-04 [patent_title] => 'Method for forming thick dielectric regions using etched trenches' [patent_app_type] => utility [patent_app_number] => 11/004694 [patent_app_country] => US [patent_app_date] => 2004-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3213 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/023/07023069.pdf [firstpage_image] =>[orig_patent_app_number] => 11004694 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/004694
Method for forming thick dielectric regions using etched trenches Dec 2, 2004 Issued
Array ( [id] => 6936529 [patent_doc_number] => 20050110090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Thin film transistor, method of fabricating the same, and flat panel display using the thin film transistor' [patent_app_type] => utility [patent_app_number] => 10/994264 [patent_app_country] => US [patent_app_date] => 2004-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3491 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20050110090.pdf [firstpage_image] =>[orig_patent_app_number] => 10994264 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/994264
Thin film transistor, method of fabricating the same, and flat panel display using the thin film transistor Nov 22, 2004 Abandoned
Array ( [id] => 4651612 [patent_doc_number] => 20080038868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'Process for Packaging Components, and Packaged Components' [patent_app_type] => utility [patent_app_number] => 10/580284 [patent_app_country] => US [patent_app_date] => 2004-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5905 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20080038868.pdf [firstpage_image] =>[orig_patent_app_number] => 10580284 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/580284
Process for packaging components, and packaged components Nov 14, 2004 Issued
Array ( [id] => 463343 [patent_doc_number] => 07238589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-03 [patent_title] => 'In-place bonding of microstructures' [patent_app_type] => utility [patent_app_number] => 10/978551 [patent_app_country] => US [patent_app_date] => 2004-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 32 [patent_no_of_words] => 4884 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/238/07238589.pdf [firstpage_image] =>[orig_patent_app_number] => 10978551 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/978551
In-place bonding of microstructures Oct 31, 2004 Issued
Array ( [id] => 6989861 [patent_doc_number] => 20050088898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'Low power flash memory cell and method' [patent_app_type] => utility [patent_app_number] => 10/976596 [patent_app_country] => US [patent_app_date] => 2004-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2735 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20050088898.pdf [firstpage_image] =>[orig_patent_app_number] => 10976596 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/976596
Low power flash memory cell and method Oct 28, 2004 Abandoned
Array ( [id] => 233128 [patent_doc_number] => 07598555 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-10-06 [patent_title] => 'MgO tunnel barriers and method of formation' [patent_app_type] => utility [patent_app_number] => 10/973954 [patent_app_country] => US [patent_app_date] => 2004-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 16658 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/598/07598555.pdf [firstpage_image] =>[orig_patent_app_number] => 10973954 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/973954
MgO tunnel barriers and method of formation Oct 24, 2004 Issued
Array ( [id] => 630375 [patent_doc_number] => 07132335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-07 [patent_title] => 'Semiconductor device with localized charge storage dielectric and method of making same' [patent_app_type] => utility [patent_app_number] => 10/965763 [patent_app_country] => US [patent_app_date] => 2004-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9590 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/132/07132335.pdf [firstpage_image] =>[orig_patent_app_number] => 10965763 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/965763
Semiconductor device with localized charge storage dielectric and method of making same Oct 17, 2004 Issued
Array ( [id] => 1002377 [patent_doc_number] => 06908831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-21 [patent_title] => 'Method for fabricating a semiconductor structure with an encapsulation of a filling which is used for filling trenches' [patent_app_type] => utility [patent_app_number] => 10/966994 [patent_app_country] => US [patent_app_date] => 2004-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2249 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/908/06908831.pdf [firstpage_image] =>[orig_patent_app_number] => 10966994 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/966994
Method for fabricating a semiconductor structure with an encapsulation of a filling which is used for filling trenches Oct 14, 2004 Issued
Array ( [id] => 4595861 [patent_doc_number] => 07981779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-19 [patent_title] => 'Method for making junction and processed material formed using the same' [patent_app_type] => utility [patent_app_number] => 10/574863 [patent_app_country] => US [patent_app_date] => 2004-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6375 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/981/07981779.pdf [firstpage_image] =>[orig_patent_app_number] => 10574863 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/574863
Method for making junction and processed material formed using the same Oct 7, 2004 Issued
Array ( [id] => 5720849 [patent_doc_number] => 20060073624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-06 [patent_title] => 'Die-attach films for chip-scale packaging, packages made therewith, and methods of assembling same' [patent_app_type] => utility [patent_app_number] => 10/956624 [patent_app_country] => US [patent_app_date] => 2004-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4840 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20060073624.pdf [firstpage_image] =>[orig_patent_app_number] => 10956624 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/956624
Die-attach films for chip-scale packaging, packages made therewith, and methods of assembling same Sep 29, 2004 Issued
Array ( [id] => 686563 [patent_doc_number] => 07078279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'Manufacturing method of a thin film transistor array substrate' [patent_app_type] => utility [patent_app_number] => 10/950493 [patent_app_country] => US [patent_app_date] => 2004-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 7236 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/078/07078279.pdf [firstpage_image] =>[orig_patent_app_number] => 10950493 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/950493
Manufacturing method of a thin film transistor array substrate Sep 27, 2004 Issued
Array ( [id] => 616353 [patent_doc_number] => 07144764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-05 [patent_title] => 'Method of manufacturing semiconductor device having trench isolation' [patent_app_type] => utility [patent_app_number] => 10/949451 [patent_app_country] => US [patent_app_date] => 2004-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 75 [patent_no_of_words] => 17425 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/144/07144764.pdf [firstpage_image] =>[orig_patent_app_number] => 10949451 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/949451
Method of manufacturing semiconductor device having trench isolation Sep 26, 2004 Issued
Array ( [id] => 612723 [patent_doc_number] => 07148120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-12 [patent_title] => 'Method of forming improved rounded corners in STI features' [patent_app_type] => utility [patent_app_number] => 10/948934 [patent_app_country] => US [patent_app_date] => 2004-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2264 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/148/07148120.pdf [firstpage_image] =>[orig_patent_app_number] => 10948934 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/948934
Method of forming improved rounded corners in STI features Sep 22, 2004 Issued
Array ( [id] => 638345 [patent_doc_number] => 07126205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-24 [patent_title] => 'Devices having improved capacitance and methods of their fabrication' [patent_app_type] => utility [patent_app_number] => 10/946770 [patent_app_country] => US [patent_app_date] => 2004-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 2694 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/126/07126205.pdf [firstpage_image] =>[orig_patent_app_number] => 10946770 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/946770
Devices having improved capacitance and methods of their fabrication Sep 21, 2004 Issued
Array ( [id] => 533695 [patent_doc_number] => 07176039 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-02-13 [patent_title] => 'Dynamic modification of gap fill process characteristics' [patent_app_type] => utility [patent_app_number] => 10/947424 [patent_app_country] => US [patent_app_date] => 2004-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5432 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/176/07176039.pdf [firstpage_image] =>[orig_patent_app_number] => 10947424 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/947424
Dynamic modification of gap fill process characteristics Sep 20, 2004 Issued
Array ( [id] => 6969698 [patent_doc_number] => 20050035408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-17 [patent_title] => 'Methods of fabricating a dielectric plug in MOSFETs to suppress short-channel effects' [patent_app_type] => utility [patent_app_number] => 10/931507 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4537 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20050035408.pdf [firstpage_image] =>[orig_patent_app_number] => 10931507 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/931507
MOSFETs including a dielectric plug to suppress short-channel effects Aug 31, 2004 Issued
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