
Benjamin E. Lanier
Examiner (ID: 11317, Phone: (571)272-3805 , Office: P/2437 )
| Most Active Art Unit | 2437 |
| Art Unit(s) | 2437, 2132, 2432 |
| Total Applications | 1337 |
| Issued Applications | 871 |
| Pending Applications | 110 |
| Abandoned Applications | 371 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6996836
[patent_doc_number] => 20050136614
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-23
[patent_title] => 'Methods of forming shallow trench isolation'
[patent_app_type] => utility
[patent_app_number] => 11/021803
[patent_app_country] => US
[patent_app_date] => 2004-12-23
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[pdf_file] => publications/A1/0136/20050136614.pdf
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Array
(
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[patent_title] => 'Fabrication method of thin film transistor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/019074 | Fabrication method of thin film transistor | Dec 20, 2004 | Issued |
Array
(
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[patent_doc_number] => 20050098774
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[patent_issue_date] => 2005-05-12
[patent_title] => 'Method of forming multiple gate insulators on a strained semiconductor heterostructure'
[patent_app_type] => utility
[patent_app_number] => 11/015266
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[patent_app_date] => 2004-12-17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/015266 | Method of forming multiple gate insulators on a strained semiconductor heterostructure | Dec 16, 2004 | Issued |
Array
(
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[patent_doc_number] => 20050287822
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[patent_issue_date] => 2005-12-29
[patent_title] => 'Method of forming polysilicon layer in semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/016413
[patent_app_country] => US
[patent_app_date] => 2004-12-17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/016413 | Method of forming polysilicon layer in semiconductor device | Dec 16, 2004 | Issued |
Array
(
[id] => 751898
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[patent_issue_date] => 2006-04-04
[patent_title] => 'Method for forming thick dielectric regions using etched trenches'
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[patent_app_number] => 11/004694
[patent_app_country] => US
[patent_app_date] => 2004-12-03
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/004694 | Method for forming thick dielectric regions using etched trenches | Dec 2, 2004 | Issued |
Array
(
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[patent_issue_date] => 2005-05-26
[patent_title] => 'Thin film transistor, method of fabricating the same, and flat panel display using the thin film transistor'
[patent_app_type] => utility
[patent_app_number] => 10/994264
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/994264 | Thin film transistor, method of fabricating the same, and flat panel display using the thin film transistor | Nov 22, 2004 | Abandoned |
Array
(
[id] => 4651612
[patent_doc_number] => 20080038868
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[patent_kind] => A1
[patent_issue_date] => 2008-02-14
[patent_title] => 'Process for Packaging Components, and Packaged Components'
[patent_app_type] => utility
[patent_app_number] => 10/580284
[patent_app_country] => US
[patent_app_date] => 2004-11-15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/580284 | Process for packaging components, and packaged components | Nov 14, 2004 | Issued |
Array
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[id] => 463343
[patent_doc_number] => 07238589
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[patent_issue_date] => 2007-07-03
[patent_title] => 'In-place bonding of microstructures'
[patent_app_type] => utility
[patent_app_number] => 10/978551
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/978551 | In-place bonding of microstructures | Oct 31, 2004 | Issued |
Array
(
[id] => 6989861
[patent_doc_number] => 20050088898
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[patent_title] => 'Low power flash memory cell and method'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/976596 | Low power flash memory cell and method | Oct 28, 2004 | Abandoned |
Array
(
[id] => 233128
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[patent_issue_date] => 2009-10-06
[patent_title] => 'MgO tunnel barriers and method of formation'
[patent_app_type] => utility
[patent_app_number] => 10/973954
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/973954 | MgO tunnel barriers and method of formation | Oct 24, 2004 | Issued |
Array
(
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[patent_title] => 'Semiconductor device with localized charge storage dielectric and method of making same'
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Array
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Array
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Array
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[patent_title] => 'Die-attach films for chip-scale packaging, packages made therewith, and methods of assembling same'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/950493 | Manufacturing method of a thin film transistor array substrate | Sep 27, 2004 | Issued |
Array
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[patent_title] => 'Method of manufacturing semiconductor device having trench isolation'
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Array
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Array
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Array
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