
Benjamin E. Lanier
Examiner (ID: 11317, Phone: (571)272-3805 , Office: P/2437 )
| Most Active Art Unit | 2437 |
| Art Unit(s) | 2437, 2132, 2432 |
| Total Applications | 1337 |
| Issued Applications | 871 |
| Pending Applications | 110 |
| Abandoned Applications | 371 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7033825
[patent_doc_number] => 20050032335
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-10
[patent_title] => 'Method to chemically remove metal impurities from polycide gate sidewalls'
[patent_app_type] => utility
[patent_app_number] => 10/929933
[patent_app_country] => US
[patent_app_date] => 2004-08-30
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[pdf_file] => publications/A1/0032/20050032335.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/929933 | Method to chemically remove metal impurities from polycide gate sidewalls | Aug 29, 2004 | Abandoned |
Array
(
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[patent_issue_date] => 2006-10-10
[patent_title] => 'Method for fabricating semiconductor device with fine patterns'
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[patent_app_date] => 2004-08-24
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/925856 | Method for fabricating semiconductor device with fine patterns | Aug 23, 2004 | Issued |
Array
(
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[patent_issue_date] => 2006-10-03
[patent_title] => 'Patterning SOI with silicon mask to create box at different depths'
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Array
(
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[patent_issue_date] => 2008-12-02
[patent_title] => 'Method to build a wirebond probe card in a many at a time fashion'
[patent_app_type] => utility
[patent_app_number] => 10/922486
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Array
(
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[patent_title] => 'Semiconductor device and its manufacturing method'
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Array
(
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[patent_title] => 'Method of controlling depth of trench in shallow trench isolation and method of forming trench for isolation using the same'
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Array
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[patent_title] => 'Methods of fabricating multiple sets of field effect transistors'
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Array
(
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[patent_title] => 'Dielectric material forming methods and enhanced dielectric materials'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/914821 | Methods of fabricating multiple sets of field effect transistors | Aug 8, 2004 | Issued |
Array
(
[id] => 915257
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[patent_title] => 'Stacked organic photosensitive devices'
[patent_app_type] => utility
[patent_app_number] => 10/911560
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/911560 | Stacked organic photosensitive devices | Aug 4, 2004 | Issued |
Array
(
[id] => 5820657
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[patent_title] => 'Method for preparing a semiconductor substrate surface for semiconductor device fabrication'
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Array
(
[id] => 530262
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Array
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Array
(
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[patent_title] => 'Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI)'
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Array
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Array
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Array
(
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/872618 | Method and apparatus for reducing charge loss in a nonvolatile memory cell | Jun 20, 2004 | Issued |