Search

Benjamin E. Lanier

Examiner (ID: 11317, Phone: (571)272-3805 , Office: P/2437 )

Most Active Art Unit
2437
Art Unit(s)
2437, 2132, 2432
Total Applications
1337
Issued Applications
871
Pending Applications
110
Abandoned Applications
371

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7033825 [patent_doc_number] => 20050032335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'Method to chemically remove metal impurities from polycide gate sidewalls' [patent_app_type] => utility [patent_app_number] => 10/929933 [patent_app_country] => US [patent_app_date] => 2004-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7278 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20050032335.pdf [firstpage_image] =>[orig_patent_app_number] => 10929933 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/929933
Method to chemically remove metal impurities from polycide gate sidewalls Aug 29, 2004 Abandoned
Array ( [id] => 645297 [patent_doc_number] => 07119013 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-10 [patent_title] => 'Method for fabricating semiconductor device with fine patterns' [patent_app_type] => utility [patent_app_number] => 10/925856 [patent_app_country] => US [patent_app_date] => 2004-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 38 [patent_no_of_words] => 15590 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/119/07119013.pdf [firstpage_image] =>[orig_patent_app_number] => 10925856 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/925856
Method for fabricating semiconductor device with fine patterns Aug 23, 2004 Issued
Array ( [id] => 7605466 [patent_doc_number] => 07115463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-03 [patent_title] => 'Patterning SOI with silicon mask to create box at different depths' [patent_app_type] => utility [patent_app_number] => 10/923246 [patent_app_country] => US [patent_app_date] => 2004-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 5100 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/115/07115463.pdf [firstpage_image] =>[orig_patent_app_number] => 10923246 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/923246
Patterning SOI with silicon mask to create box at different depths Aug 19, 2004 Issued
Array ( [id] => 579285 [patent_doc_number] => 07459795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-02 [patent_title] => 'Method to build a wirebond probe card in a many at a time fashion' [patent_app_type] => utility [patent_app_number] => 10/922486 [patent_app_country] => US [patent_app_date] => 2004-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 29 [patent_no_of_words] => 6049 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/459/07459795.pdf [firstpage_image] =>[orig_patent_app_number] => 10922486 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/922486
Method to build a wirebond probe card in a many at a time fashion Aug 18, 2004 Issued
Array ( [id] => 591367 [patent_doc_number] => 07439602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-21 [patent_title] => 'Semiconductor device and its manufacturing method' [patent_app_type] => utility [patent_app_number] => 10/915773 [patent_app_country] => US [patent_app_date] => 2004-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5806 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/439/07439602.pdf [firstpage_image] =>[orig_patent_app_number] => 10915773 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/915773
Semiconductor device and its manufacturing method Aug 10, 2004 Issued
Array ( [id] => 7203936 [patent_doc_number] => 20050042837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Method of controlling depth of trench in shallow trench isolation and method of forming trench for isolation using the same' [patent_app_type] => utility [patent_app_number] => 10/916304 [patent_app_country] => US [patent_app_date] => 2004-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2706 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20050042837.pdf [firstpage_image] =>[orig_patent_app_number] => 10916304 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/916304
Method of controlling depth of trench in shallow trench isolation and method of forming trench for isolation using the same Aug 9, 2004 Abandoned
Array ( [id] => 707633 [patent_doc_number] => 07060570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-13 [patent_title] => 'Methods of fabricating multiple sets of field effect transistors' [patent_app_type] => utility [patent_app_number] => 10/914825 [patent_app_country] => US [patent_app_date] => 2004-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2743 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/060/07060570.pdf [firstpage_image] =>[orig_patent_app_number] => 10914825 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/914825
Methods of fabricating multiple sets of field effect transistors Aug 8, 2004 Issued
Array ( [id] => 715475 [patent_doc_number] => 07052953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-30 [patent_title] => 'Dielectric material forming methods and enhanced dielectric materials' [patent_app_type] => utility [patent_app_number] => 10/914888 [patent_app_country] => US [patent_app_date] => 2004-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4215 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/052/07052953.pdf [firstpage_image] =>[orig_patent_app_number] => 10914888 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/914888
Dielectric material forming methods and enhanced dielectric materials Aug 8, 2004 Issued
Array ( [id] => 707632 [patent_doc_number] => 07060569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-13 [patent_title] => 'Methods of fabricating multiple sets of field effect transistors' [patent_app_type] => utility [patent_app_number] => 10/914821 [patent_app_country] => US [patent_app_date] => 2004-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2743 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/060/07060569.pdf [firstpage_image] =>[orig_patent_app_number] => 10914821 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/914821
Methods of fabricating multiple sets of field effect transistors Aug 8, 2004 Issued
Array ( [id] => 915257 [patent_doc_number] => 07326955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-05 [patent_title] => 'Stacked organic photosensitive devices' [patent_app_type] => utility [patent_app_number] => 10/911560 [patent_app_country] => US [patent_app_date] => 2004-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13884 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/326/07326955.pdf [firstpage_image] =>[orig_patent_app_number] => 10911560 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/911560
Stacked organic photosensitive devices Aug 4, 2004 Issued
Array ( [id] => 5820657 [patent_doc_number] => 20060024970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Method for preparing a semiconductor substrate surface for semiconductor device fabrication' [patent_app_type] => utility [patent_app_number] => 10/901589 [patent_app_country] => US [patent_app_date] => 2004-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2842 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20060024970.pdf [firstpage_image] =>[orig_patent_app_number] => 10901589 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/901589
Method for preparing a semiconductor substrate surface for semiconductor device fabrication Jul 28, 2004 Issued
Array ( [id] => 530262 [patent_doc_number] => 07179666 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Method for manufacturing an electronic circuit device and electronic circuit device' [patent_app_type] => utility [patent_app_number] => 10/901750 [patent_app_country] => US [patent_app_date] => 2004-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 5002 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/179/07179666.pdf [firstpage_image] =>[orig_patent_app_number] => 10901750 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/901750
Method for manufacturing an electronic circuit device and electronic circuit device Jul 28, 2004 Issued
Array ( [id] => 724360 [patent_doc_number] => 07045410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Method to design for or modulate the CMOS transistor threshold voltage using shallow trench isolation (STI)' [patent_app_type] => utility [patent_app_number] => 10/899844 [patent_app_country] => US [patent_app_date] => 2004-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 6140 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/045/07045410.pdf [firstpage_image] =>[orig_patent_app_number] => 10899844 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/899844
Method to design for or modulate the CMOS transistor threshold voltage using shallow trench isolation (STI) Jul 26, 2004 Issued
Array ( [id] => 724448 [patent_doc_number] => 07045436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI)' [patent_app_type] => utility [patent_app_number] => 10/899664 [patent_app_country] => US [patent_app_date] => 2004-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 26 [patent_no_of_words] => 6698 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/045/07045436.pdf [firstpage_image] =>[orig_patent_app_number] => 10899664 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/899664
Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI) Jul 26, 2004 Issued
Array ( [id] => 740822 [patent_doc_number] => 07029929 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-18 [patent_title] => 'Method of manufacturing semiconductor devices using a bond program verification system' [patent_app_type] => utility [patent_app_number] => 10/897520 [patent_app_country] => US [patent_app_date] => 2004-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4997 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/029/07029929.pdf [firstpage_image] =>[orig_patent_app_number] => 10897520 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/897520
Method of manufacturing semiconductor devices using a bond program verification system Jul 21, 2004 Issued
Array ( [id] => 849112 [patent_doc_number] => 07381630 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-03 [patent_title] => 'Method for integrating MEMS device and interposer' [patent_app_type] => utility [patent_app_number] => 10/889868 [patent_app_country] => US [patent_app_date] => 2004-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4939 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/381/07381630.pdf [firstpage_image] =>[orig_patent_app_number] => 10889868 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/889868
Method for integrating MEMS device and interposer Jul 12, 2004 Issued
Array ( [id] => 956224 [patent_doc_number] => 06955974 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-18 [patent_title] => 'Method for forming isolation layer of semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/877714 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2093 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/955/06955974.pdf [firstpage_image] =>[orig_patent_app_number] => 10877714 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/877714
Method for forming isolation layer of semiconductor device Jun 24, 2004 Issued
Array ( [id] => 7097974 [patent_doc_number] => 20050130433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Method of forming isolation film in semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/876333 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2421 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20050130433.pdf [firstpage_image] =>[orig_patent_app_number] => 10876333 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/876333
Method of forming isolation film in semiconductor device Jun 23, 2004 Issued
Array ( [id] => 7407687 [patent_doc_number] => 20040227260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Semiconductor device using fuse/anti-fuse system and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/872506 [patent_app_country] => US [patent_app_date] => 2004-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8329 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20040227260.pdf [firstpage_image] =>[orig_patent_app_number] => 10872506 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/872506
Semiconductor device using fuse/anti-fuse system and method of manufacturing the same Jun 21, 2004 Abandoned
Array ( [id] => 401182 [patent_doc_number] => 07291546 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-11-06 [patent_title] => 'Method and apparatus for reducing charge loss in a nonvolatile memory cell' [patent_app_type] => utility [patent_app_number] => 10/872618 [patent_app_country] => US [patent_app_date] => 2004-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3345 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/291/07291546.pdf [firstpage_image] =>[orig_patent_app_number] => 10872618 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/872618
Method and apparatus for reducing charge loss in a nonvolatile memory cell Jun 20, 2004 Issued
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