
Benjamin E. Lanier
Examiner (ID: 11317, Phone: (571)272-3805 , Office: P/2437 )
| Most Active Art Unit | 2437 |
| Art Unit(s) | 2437, 2132, 2432 |
| Total Applications | 1337 |
| Issued Applications | 871 |
| Pending Applications | 110 |
| Abandoned Applications | 371 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7349172
[patent_doc_number] => 20040248393
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-09
[patent_title] => 'Method of manufacturing semiconductor device and the semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/867765
[patent_app_country] => US
[patent_app_date] => 2004-06-16
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[pdf_file] => publications/A1/0248/20040248393.pdf
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Array
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[patent_title] => 'PE-ALD of TaN diffusion barrier region on low-k materials'
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Array
(
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[patent_issue_date] => 2005-01-06
[patent_title] => 'Method of and apparatus for manufacturing semiconductor thin film, and method of manufacturing thin film transistor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/856275 | Method of and apparatus for manufacturing semiconductor thin film, and method of manufacturing thin film transistor | May 27, 2004 | Issued |
Array
(
[id] => 5780133
[patent_doc_number] => 20060202228
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[patent_issue_date] => 2006-09-14
[patent_title] => 'Semiconductor device'
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Array
(
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[patent_title] => 'Low voltage power MOSFET device and process for its manufacture'
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Array
(
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[patent_title] => 'Method utilizing compensation features in semiconductor processing'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/842065 | Method utilizing compensation features in semiconductor processing | May 9, 2004 | Issued |
Array
(
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[patent_title] => 'Fill for large volume vias'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/841136 | Fill for large volume vias | May 6, 2004 | Abandoned |
Array
(
[id] => 864445
[patent_doc_number] => 07368298
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[patent_issue_date] => 2008-05-06
[patent_title] => 'Method of manufacturing ferroelectric semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/835436
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10835436
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/835436 | Method of manufacturing ferroelectric semiconductor device | Apr 29, 2004 | Issued |
Array
(
[id] => 830099
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[patent_issue_date] => 2008-07-15
[patent_title] => 'Method for manufacturing a micro-electro-mechanical device, in particular an optical microswitch, and micro-electro-mechanical device thus obtained'
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[patent_app_number] => 10/821263
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/821263 | Method for manufacturing a micro-electro-mechanical device, in particular an optical microswitch, and micro-electro-mechanical device thus obtained | Apr 7, 2004 | Issued |
Array
(
[id] => 401177
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[patent_title] => 'System and method for providing improved trench isolation of semiconductor devices'
[patent_app_type] => utility
[patent_app_number] => 10/803273
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Array
(
[id] => 951312
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[patent_title] => 'Pitcher-shaped active area for field effect transistor and method of forming same'
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Array
(
[id] => 475039
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[patent_title] => 'Fabrication method for a multi-layered thin film protective layer'
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Array
(
[id] => 7465523
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[patent_title] => 'A METHOD OF PRODUCING A THIN LAYER OF SEMICONDUCTOR MATERIAL'
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Array
(
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[patent_title] => 'High electrical quality buried oxide in simox'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/738783 | Vertical NROM NAND flash memory array | Dec 16, 2003 | Issued |
Array
(
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/651423 | Method for controlling the temperature of a gas distribution plate in a process reactor | Aug 28, 2003 | Issued |