Search

Benjamin E. Lanier

Examiner (ID: 11317, Phone: (571)272-3805 , Office: P/2437 )

Most Active Art Unit
2437
Art Unit(s)
2437, 2132, 2432
Total Applications
1337
Issued Applications
871
Pending Applications
110
Abandoned Applications
371

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7631020 [patent_doc_number] => 06635912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-21 [patent_title] => 'CMOS image sensor and manufacturing method thereof' [patent_app_type] => B2 [patent_app_number] => 09/947343 [patent_app_country] => US [patent_app_date] => 2001-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 33 [patent_no_of_words] => 4629 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/635/06635912.pdf [firstpage_image] =>[orig_patent_app_number] => 09947343 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/947343
CMOS image sensor and manufacturing method thereof Sep 6, 2001 Issued
Array ( [id] => 1416046 [patent_doc_number] => 06518148 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Method for protecting STI structures with low etching rate liners' [patent_app_type] => B1 [patent_app_number] => 09/947634 [patent_app_country] => US [patent_app_date] => 2001-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2936 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/518/06518148.pdf [firstpage_image] =>[orig_patent_app_number] => 09947634 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/947634
Method for protecting STI structures with low etching rate liners Sep 5, 2001 Issued
Array ( [id] => 6750598 [patent_doc_number] => 20030045118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Method for controlling the critical dimension of the polysilicon gate by etching the hard mask' [patent_app_type] => new [patent_app_number] => 09/945653 [patent_app_country] => US [patent_app_date] => 2001-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2612 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20030045118.pdf [firstpage_image] =>[orig_patent_app_number] => 09945653 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/945653
Method for controlling the critical dimension of the polysilicon gate by etching the hard mask Sep 4, 2001 Abandoned
Array ( [id] => 1139475 [patent_doc_number] => 06789235 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-07 [patent_title] => 'Bond program verification system' [patent_app_type] => B1 [patent_app_number] => 09/947339 [patent_app_country] => US [patent_app_date] => 2001-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4820 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/789/06789235.pdf [firstpage_image] =>[orig_patent_app_number] => 09947339 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/947339
Bond program verification system Sep 4, 2001 Issued
Array ( [id] => 6750605 [patent_doc_number] => 20030045125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Nitrogen containing plasma annealing method for forming a nitrogenated silicon carbide layer' [patent_app_type] => new [patent_app_number] => 09/946904 [patent_app_country] => US [patent_app_date] => 2001-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5488 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20030045125.pdf [firstpage_image] =>[orig_patent_app_number] => 09946904 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/946904
Nitrogen containing plasma annealing method for forming a nitrogenated silicon carbide layer Sep 4, 2001 Abandoned
Array ( [id] => 779209 [patent_doc_number] => 06995076 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-07 [patent_title] => 'Relaxed SiGe films by surfactant mediation' [patent_app_type] => utility [patent_app_number] => 09/947774 [patent_app_country] => US [patent_app_date] => 2001-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 2899 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/995/06995076.pdf [firstpage_image] =>[orig_patent_app_number] => 09947774 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/947774
Relaxed SiGe films by surfactant mediation Sep 4, 2001 Issued
Array ( [id] => 6000062 [patent_doc_number] => 20020028573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-07 [patent_title] => 'Automatic wiring method for semiconductor package enabling design of high-speed wiring for semiconductor package with reduced labor' [patent_app_type] => new [patent_app_number] => 09/945964 [patent_app_country] => US [patent_app_date] => 2001-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 4587 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20020028573.pdf [firstpage_image] =>[orig_patent_app_number] => 09945964 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/945964
Automatic wiring method for semiconductor package enabling design of high-speed wiring for semiconductor package with reduced labor Sep 3, 2001 Issued
Array ( [id] => 6748085 [patent_doc_number] => 20030042605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Concentration graded carbon doped oxide' [patent_app_type] => new [patent_app_number] => 09/943874 [patent_app_country] => US [patent_app_date] => 2001-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2163 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20030042605.pdf [firstpage_image] =>[orig_patent_app_number] => 09943874 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/943874
Concentration graded carbon doped oxide Aug 30, 2001 Issued
Array ( [id] => 6748025 [patent_doc_number] => 20030042545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Method of forming multi-layers for a thin film transistor (TFT) and the device formed thereby' [patent_app_type] => new [patent_app_number] => 09/945063 [patent_app_country] => US [patent_app_date] => 2001-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2701 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20030042545.pdf [firstpage_image] =>[orig_patent_app_number] => 09945063 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/945063
Method of forming multi-layers for a thin film transistor Aug 30, 2001 Issued
Array ( [id] => 876163 [patent_doc_number] => 07358171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-15 [patent_title] => 'Method to chemically remove metal impurities from polycide gate sidewalls' [patent_app_type] => utility [patent_app_number] => 09/945553 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7276 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/358/07358171.pdf [firstpage_image] =>[orig_patent_app_number] => 09945553 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/945553
Method to chemically remove metal impurities from polycide gate sidewalls Aug 29, 2001 Issued
Array ( [id] => 6306673 [patent_doc_number] => 20020094633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-18 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/943843 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6150 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20020094633.pdf [firstpage_image] =>[orig_patent_app_number] => 09943843 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/943843
Semiconductor device and method of manufacturing the same Aug 29, 2001 Issued
Array ( [id] => 6750528 [patent_doc_number] => 20030045048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Dielectric material forming methods and enhanced dielectric materials' [patent_app_type] => new [patent_app_number] => 09/945393 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4238 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20030045048.pdf [firstpage_image] =>[orig_patent_app_number] => 09945393 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/945393
Dielectric material forming methods Aug 29, 2001 Issued
Array ( [id] => 5951449 [patent_doc_number] => 20020006687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-17 [patent_title] => 'Integrated IC chip package for electronic image sensor die' [patent_app_type] => new [patent_app_number] => 09/943804 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4183 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20020006687.pdf [firstpage_image] =>[orig_patent_app_number] => 09943804 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/943804
Integrated IC chip package for electronic image sensor die Aug 29, 2001 Issued
Array ( [id] => 6221925 [patent_doc_number] => 20020003277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'Technique for forming shallow trench isolation structure without corner exposure and resulting structure' [patent_app_type] => new [patent_app_number] => 09/944506 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2157 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20020003277.pdf [firstpage_image] =>[orig_patent_app_number] => 09944506 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/944506
Technique for forming shallow trench isolation structure without corner exposure and resulting structure Aug 29, 2001 Abandoned
Array ( [id] => 5874131 [patent_doc_number] => 20020048946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Local interconnect structures for integrated circuits and methods for making the same' [patent_app_type] => new [patent_app_number] => 09/943994 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3270 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20020048946.pdf [firstpage_image] =>[orig_patent_app_number] => 09943994 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/943994
Local interconnect structures for integrated circuits and methods for making the same Aug 29, 2001 Issued
Array ( [id] => 6748086 [patent_doc_number] => 20030042606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Method of forming a conductive contact' [patent_app_type] => new [patent_app_number] => 09/941533 [patent_app_country] => US [patent_app_date] => 2001-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6487 [patent_no_of_claims] => 100 [patent_no_of_ind_claims] => 25 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20030042606.pdf [firstpage_image] =>[orig_patent_app_number] => 09941533 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/941533
Method of forming a conductive contact Aug 28, 2001 Issued
Array ( [id] => 6469294 [patent_doc_number] => 20020023590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => 'Susceptor for semiconductor wafers' [patent_app_type] => new [patent_app_number] => 09/941824 [patent_app_country] => US [patent_app_date] => 2001-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2134 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20020023590.pdf [firstpage_image] =>[orig_patent_app_number] => 09941824 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/941824
Susceptor for semiconductor wafers Aug 28, 2001 Abandoned
Array ( [id] => 1253312 [patent_doc_number] => 06670235 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-30 [patent_title] => 'Process flow for two-step collar in DRAM preparation' [patent_app_type] => B1 [patent_app_number] => 09/939554 [patent_app_country] => US [patent_app_date] => 2001-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2504 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/670/06670235.pdf [firstpage_image] =>[orig_patent_app_number] => 09939554 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/939554
Process flow for two-step collar in DRAM preparation Aug 27, 2001 Issued
Array ( [id] => 6224578 [patent_doc_number] => 20020004251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'Method of making a semiconductor radiation emitter package' [patent_app_type] => new [patent_app_number] => 09/935443 [patent_app_country] => US [patent_app_date] => 2001-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 19756 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20020004251.pdf [firstpage_image] =>[orig_patent_app_number] => 09935443 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/935443
Method of making a semiconductor radiation emitter package Aug 22, 2001 Issued
Array ( [id] => 6503215 [patent_doc_number] => 20020025656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => 'Semiconductor chip pick-up method' [patent_app_type] => new [patent_app_number] => 09/929103 [patent_app_country] => US [patent_app_date] => 2001-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4642 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20020025656.pdf [firstpage_image] =>[orig_patent_app_number] => 09929103 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/929103
Semiconductor chip pick-up method Aug 14, 2001 Issued
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