
Benjamin E. Lanier
Examiner (ID: 11317, Phone: (571)272-3805 , Office: P/2437 )
| Most Active Art Unit | 2437 |
| Art Unit(s) | 2437, 2132, 2432 |
| Total Applications | 1337 |
| Issued Applications | 871 |
| Pending Applications | 110 |
| Abandoned Applications | 371 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7631020
[patent_doc_number] => 06635912
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-10-21
[patent_title] => 'CMOS image sensor and manufacturing method thereof'
[patent_app_type] => B2
[patent_app_number] => 09/947343
[patent_app_country] => US
[patent_app_date] => 2001-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 33
[patent_no_of_words] => 4629
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/635/06635912.pdf
[firstpage_image] =>[orig_patent_app_number] => 09947343
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/947343 | CMOS image sensor and manufacturing method thereof | Sep 6, 2001 | Issued |
Array
(
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[patent_doc_number] => 06518148
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[patent_kind] => B1
[patent_issue_date] => 2003-02-11
[patent_title] => 'Method for protecting STI structures with low etching rate liners'
[patent_app_type] => B1
[patent_app_number] => 09/947634
[patent_app_country] => US
[patent_app_date] => 2001-09-06
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Array
(
[id] => 6750598
[patent_doc_number] => 20030045118
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-03-06
[patent_title] => 'Method for controlling the critical dimension of the polysilicon gate by etching the hard mask'
[patent_app_type] => new
[patent_app_number] => 09/945653
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[pdf_file] => publications/A1/0045/20030045118.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/945653 | Method for controlling the critical dimension of the polysilicon gate by etching the hard mask | Sep 4, 2001 | Abandoned |
Array
(
[id] => 1139475
[patent_doc_number] => 06789235
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[patent_kind] => B1
[patent_issue_date] => 2004-09-07
[patent_title] => 'Bond program verification system'
[patent_app_type] => B1
[patent_app_number] => 09/947339
[patent_app_country] => US
[patent_app_date] => 2001-09-05
[patent_effective_date] => 0000-00-00
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Array
(
[id] => 6750605
[patent_doc_number] => 20030045125
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[patent_issue_date] => 2003-03-06
[patent_title] => 'Nitrogen containing plasma annealing method for forming a nitrogenated silicon carbide layer'
[patent_app_type] => new
[patent_app_number] => 09/946904
[patent_app_country] => US
[patent_app_date] => 2001-09-05
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Array
(
[id] => 779209
[patent_doc_number] => 06995076
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-07
[patent_title] => 'Relaxed SiGe films by surfactant mediation'
[patent_app_type] => utility
[patent_app_number] => 09/947774
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 09947774
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/947774 | Relaxed SiGe films by surfactant mediation | Sep 4, 2001 | Issued |
Array
(
[id] => 6000062
[patent_doc_number] => 20020028573
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[patent_issue_date] => 2002-03-07
[patent_title] => 'Automatic wiring method for semiconductor package enabling design of high-speed wiring for semiconductor package with reduced labor'
[patent_app_type] => new
[patent_app_number] => 09/945964
[patent_app_country] => US
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[pdf_file] => publications/A1/0028/20020028573.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/945964 | Automatic wiring method for semiconductor package enabling design of high-speed wiring for semiconductor package with reduced labor | Sep 3, 2001 | Issued |
Array
(
[id] => 6748085
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[patent_issue_date] => 2003-03-06
[patent_title] => 'Concentration graded carbon doped oxide'
[patent_app_type] => new
[patent_app_number] => 09/943874
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/943874 | Concentration graded carbon doped oxide | Aug 30, 2001 | Issued |
Array
(
[id] => 6748025
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[patent_title] => 'Method of forming multi-layers for a thin film transistor (TFT) and the device formed thereby'
[patent_app_type] => new
[patent_app_number] => 09/945063
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/945063 | Method of forming multi-layers for a thin film transistor | Aug 30, 2001 | Issued |
Array
(
[id] => 876163
[patent_doc_number] => 07358171
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[patent_issue_date] => 2008-04-15
[patent_title] => 'Method to chemically remove metal impurities from polycide gate sidewalls'
[patent_app_type] => utility
[patent_app_number] => 09/945553
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/945553 | Method to chemically remove metal impurities from polycide gate sidewalls | Aug 29, 2001 | Issued |
Array
(
[id] => 6306673
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[patent_issue_date] => 2002-07-18
[patent_title] => 'Semiconductor device and method of manufacturing the same'
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Array
(
[id] => 6750528
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[patent_title] => 'Dielectric material forming methods and enhanced dielectric materials'
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Array
(
[id] => 5951449
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Array
(
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Array
(
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Array
(
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Array
(
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/929103 | Semiconductor chip pick-up method | Aug 14, 2001 | Issued |