
Benjamin E. Lanier
Examiner (ID: 11317, Phone: (571)272-3805 , Office: P/2437 )
| Most Active Art Unit | 2437 |
| Art Unit(s) | 2437, 2132, 2432 |
| Total Applications | 1337 |
| Issued Applications | 871 |
| Pending Applications | 110 |
| Abandoned Applications | 371 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6934481
[patent_doc_number] => 20010055825
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-12-27
[patent_title] => 'Laser marking techniques'
[patent_app_type] => new
[patent_app_number] => 09/928314
[patent_app_country] => US
[patent_app_date] => 2001-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4713
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 32
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0055/20010055825.pdf
[firstpage_image] =>[orig_patent_app_number] => 09928314
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/928314 | Laser marking techniques | Aug 12, 2001 | Abandoned |
Array
(
[id] => 1280814
[patent_doc_number] => 06642078
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-11-04
[patent_title] => 'Method for manufacturing diode subassemblies used in rectifier assemblies of engine driven generators'
[patent_app_type] => B2
[patent_app_number] => 09/928974
[patent_app_country] => US
[patent_app_date] => 2001-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 30
[patent_no_of_words] => 3773
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/642/06642078.pdf
[firstpage_image] =>[orig_patent_app_number] => 09928974
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/928974 | Method for manufacturing diode subassemblies used in rectifier assemblies of engine driven generators | Aug 12, 2001 | Issued |
Array
(
[id] => 6556106
[patent_doc_number] => 20020164424
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-07
[patent_title] => 'Method for fabricating N-type doped polycrystalline silicon'
[patent_app_type] => new
[patent_app_number] => 09/922253
[patent_app_country] => US
[patent_app_date] => 2001-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1566
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0164/20020164424.pdf
[firstpage_image] =>[orig_patent_app_number] => 09922253
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/922253 | Method for fabricating N-type doped polycrystalline silicon | Aug 2, 2001 | Abandoned |
Array
(
[id] => 1128472
[patent_doc_number] => 06786978
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-09-07
[patent_title] => 'Mass production of cross-section TEM samples by focused ion beam deposition and anisotropic etching'
[patent_app_type] => B2
[patent_app_number] => 09/921324
[patent_app_country] => US
[patent_app_date] => 2001-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2818
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/786/06786978.pdf
[firstpage_image] =>[orig_patent_app_number] => 09921324
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/921324 | Mass production of cross-section TEM samples by focused ion beam deposition and anisotropic etching | Aug 1, 2001 | Issued |
Array
(
[id] => 990740
[patent_doc_number] => 06919266
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-07-19
[patent_title] => 'Copper technology for ULSI metallization'
[patent_app_type] => utility
[patent_app_number] => 09/910914
[patent_app_country] => US
[patent_app_date] => 2001-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 18
[patent_no_of_words] => 3979
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/919/06919266.pdf
[firstpage_image] =>[orig_patent_app_number] => 09910914
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/910914 | Copper technology for ULSI metallization | Jul 23, 2001 | Issued |
Array
(
[id] => 7629885
[patent_doc_number] => 06818470
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-11-16
[patent_title] => 'Process for producing a thermoelectric converter'
[patent_app_type] => B1
[patent_app_number] => 09/806424
[patent_app_country] => US
[patent_app_date] => 2001-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 22
[patent_no_of_words] => 3062
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/818/06818470.pdf
[firstpage_image] =>[orig_patent_app_number] => 09806424
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/806424 | Process for producing a thermoelectric converter | Jul 23, 2001 | Issued |
Array
(
[id] => 6772434
[patent_doc_number] => 20030015772
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-23
[patent_title] => 'Method and structure for DC and RF shielding of integrated circuits'
[patent_app_type] => new
[patent_app_number] => 09/911364
[patent_app_country] => US
[patent_app_date] => 2001-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4265
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 35
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0015/20030015772.pdf
[firstpage_image] =>[orig_patent_app_number] => 09911364
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/911364 | Method and structure for DC and RF shielding of integrated circuits | Jul 22, 2001 | Issued |
Array
(
[id] => 6898581
[patent_doc_number] => 20010046746
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-11-29
[patent_title] => 'Method of fabricating an SOI wafer and SOI wafer fabricated by the method'
[patent_app_type] => new
[patent_app_number] => 09/906873
[patent_app_country] => US
[patent_app_date] => 2001-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 4563
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 30
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0046/20010046746.pdf
[firstpage_image] =>[orig_patent_app_number] => 09906873
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/906873 | Method of fabricating an SOI wafer and SOI wafer fabricated by the method | Jul 15, 2001 | Abandoned |
Array
(
[id] => 1145926
[patent_doc_number] => 06773939
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-08-10
[patent_title] => 'Method and apparatus for determining critical dimension variation in a line structure'
[patent_app_type] => B1
[patent_app_number] => 09/897624
[patent_app_country] => US
[patent_app_date] => 2001-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 4313
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/773/06773939.pdf
[firstpage_image] =>[orig_patent_app_number] => 09897624
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/897624 | Method and apparatus for determining critical dimension variation in a line structure | Jul 1, 2001 | Issued |
Array
(
[id] => 1119747
[patent_doc_number] => 06797586
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-09-28
[patent_title] => 'Silicon carbide schottky barrier diode and method of making'
[patent_app_type] => B2
[patent_app_number] => 09/894084
[patent_app_country] => US
[patent_app_date] => 2001-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 1817
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/797/06797586.pdf
[firstpage_image] =>[orig_patent_app_number] => 09894084
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/894084 | Silicon carbide schottky barrier diode and method of making | Jun 27, 2001 | Issued |
Array
(
[id] => 5888716
[patent_doc_number] => 20020013044
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-31
[patent_title] => 'HDP liner layer prior to HSQ/SOG deposition to reduce the amount of HSQ/SOG over the metal lead'
[patent_app_type] => new
[patent_app_number] => 09/895524
[patent_app_country] => US
[patent_app_date] => 2001-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1926
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0013/20020013044.pdf
[firstpage_image] =>[orig_patent_app_number] => 09895524
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/895524 | HDP liner layer prior to HSQ/SOG deposition to reduce the amount of HSQ/SOG over the metal lead | Jun 27, 2001 | Abandoned |
Array
(
[id] => 711064
[patent_doc_number] => 07061954
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-13
[patent_title] => 'Semiconductor optical waveguide structure'
[patent_app_type] => utility
[patent_app_number] => 09/888930
[patent_app_country] => US
[patent_app_date] => 2001-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 31
[patent_no_of_words] => 6693
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/061/07061954.pdf
[firstpage_image] =>[orig_patent_app_number] => 09888930
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/888930 | Semiconductor optical waveguide structure | Jun 24, 2001 | Issued |
Array
(
[id] => 6473912
[patent_doc_number] => 20020022296
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-02-21
[patent_title] => 'Method of manufacturing a charge-coupled image sensor'
[patent_app_type] => new
[patent_app_number] => 09/888463
[patent_app_country] => US
[patent_app_date] => 2001-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2417
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0022/20020022296.pdf
[firstpage_image] =>[orig_patent_app_number] => 09888463
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/888463 | Method of manufacturing a charge-coupled image sensor | Jun 24, 2001 | Abandoned |
Array
(
[id] => 1550351
[patent_doc_number] => 06399455
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-04
[patent_title] => 'Method of fabricating a bipolar transistor with ultra small polysilicon emitter'
[patent_app_type] => B1
[patent_app_number] => 09/881904
[patent_app_country] => US
[patent_app_date] => 2001-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 7
[patent_no_of_words] => 1827
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 289
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/399/06399455.pdf
[firstpage_image] =>[orig_patent_app_number] => 09881904
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/881904 | Method of fabricating a bipolar transistor with ultra small polysilicon emitter | Jun 14, 2001 | Issued |
Array
(
[id] => 1332075
[patent_doc_number] => 06596570
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-07-22
[patent_title] => 'SOI device with reduced junction capacitance'
[patent_app_type] => B2
[patent_app_number] => 09/681794
[patent_app_country] => US
[patent_app_date] => 2001-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 16
[patent_no_of_words] => 3657
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/596/06596570.pdf
[firstpage_image] =>[orig_patent_app_number] => 09681794
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/681794 | SOI device with reduced junction capacitance | Jun 5, 2001 | Issued |
Array
(
[id] => 1128346
[patent_doc_number] => 06786936
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-09-07
[patent_title] => 'Methods, complexes, and systems for forming metal-containing films on semiconductor structures'
[patent_app_type] => B2
[patent_app_number] => 09/865612
[patent_app_country] => US
[patent_app_date] => 2001-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5764
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/786/06786936.pdf
[firstpage_image] =>[orig_patent_app_number] => 09865612
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/865612 | Methods, complexes, and systems for forming metal-containing films on semiconductor structures | May 24, 2001 | Issued |
Array
(
[id] => 6921600
[patent_doc_number] => 20010029085
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-10-11
[patent_title] => 'Methods of forming field oxide and active area regions on a semiconductor substrate'
[patent_app_type] => new
[patent_app_number] => 09/855593
[patent_app_country] => US
[patent_app_date] => 2001-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2537
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0029/20010029085.pdf
[firstpage_image] =>[orig_patent_app_number] => 09855593
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/855593 | Methods of forming field oxide and active area regions on a semiconductor substrate | May 13, 2001 | Issued |
Array
(
[id] => 6221951
[patent_doc_number] => 20020003290
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-10
[patent_title] => 'Semiconductor devices and methods for manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 09/847163
[patent_app_country] => US
[patent_app_date] => 2001-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5460
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0003/20020003290.pdf
[firstpage_image] =>[orig_patent_app_number] => 09847163
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/847163 | Semiconductor devices and methods for manufacturing the same | Apr 30, 2001 | Issued |
Array
(
[id] => 6176827
[patent_doc_number] => 20020155708
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-24
[patent_title] => 'Dielectric anti-reflective coating surface treatment to prevent defect generation in associated wet clean'
[patent_app_type] => new
[patent_app_number] => 09/838084
[patent_app_country] => US
[patent_app_date] => 2001-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2947
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0155/20020155708.pdf
[firstpage_image] =>[orig_patent_app_number] => 09838084
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/838084 | Dielectric anti-reflective coating surface treatment to prevent defect generation in associated wet clean | Apr 17, 2001 | Issued |
Array
(
[id] => 6176869
[patent_doc_number] => 20020155721
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-24
[patent_title] => 'Method of forming shallow trench isolation structure'
[patent_app_type] => new
[patent_app_number] => 09/824014
[patent_app_country] => US
[patent_app_date] => 2001-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2514
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0155/20020155721.pdf
[firstpage_image] =>[orig_patent_app_number] => 09824014
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/824014 | Method of forming shallow trench isolation structure | Apr 2, 2001 | Abandoned |