Search

Benjamin F. Fiorello

Examiner (ID: 15277, Phone: (571)270-7012 , Office: P/3678 )

Most Active Art Unit
3678
Art Unit(s)
3678, 3672, 4155
Total Applications
1365
Issued Applications
994
Pending Applications
103
Abandoned Applications
294

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7261899 [patent_doc_number] => 20040260877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Apparatus and method for renaming a cache line' [patent_app_type] => new [patent_app_number] => 10/464353 [patent_app_country] => US [patent_app_date] => 2003-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15530 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20040260877.pdf [firstpage_image] =>[orig_patent_app_number] => 10464353 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/464353
Apparatus and method for renaming a cache line Jun 18, 2003 Issued
Array ( [id] => 7358615 [patent_doc_number] => 20040250036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Trusted data store for use in connection with trusted computer operating system' [patent_app_type] => new [patent_app_number] => 10/456124 [patent_app_country] => US [patent_app_date] => 2003-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8470 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20040250036.pdf [firstpage_image] =>[orig_patent_app_number] => 10456124 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/456124
Trusted data store for use in connection with trusted computer operating system Jun 5, 2003 Issued
Array ( [id] => 503815 [patent_doc_number] => 07213127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-01 [patent_title] => 'System for producing addresses for a digital signal processor' [patent_app_type] => utility [patent_app_number] => 10/455808 [patent_app_country] => US [patent_app_date] => 2003-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4376 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/213/07213127.pdf [firstpage_image] =>[orig_patent_app_number] => 10455808 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/455808
System for producing addresses for a digital signal processor Jun 5, 2003 Issued
Array ( [id] => 7358609 [patent_doc_number] => 20040250035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Method and apparatus for affecting computer system' [patent_app_type] => new [patent_app_number] => 10/456114 [patent_app_country] => US [patent_app_date] => 2003-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3381 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20040250035.pdf [firstpage_image] =>[orig_patent_app_number] => 10456114 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/456114
Method and apparatus for affecting computer system Jun 5, 2003 Abandoned
Array ( [id] => 7266394 [patent_doc_number] => 20040243766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Writing cached data to system management memory' [patent_app_type] => new [patent_app_number] => 10/449244 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2560 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20040243766.pdf [firstpage_image] =>[orig_patent_app_number] => 10449244 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/449244
Writing cached data to system management memory May 29, 2003 Issued
Array ( [id] => 7457385 [patent_doc_number] => 20040010668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-15 [patent_title] => 'Backup technique for data stored on multiple storage devices' [patent_app_type] => new [patent_app_number] => 10/448519 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4775 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20040010668.pdf [firstpage_image] =>[orig_patent_app_number] => 10448519 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/448519
Backup technique for data stored on multiple storage devices May 29, 2003 Issued
Array ( [id] => 7266456 [patent_doc_number] => 20040243784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Method and apparatus for generating generic descrambled data patterns for testing ECC protected memory' [patent_app_type] => new [patent_app_number] => 10/448835 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5260 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20040243784.pdf [firstpage_image] =>[orig_patent_app_number] => 10448835 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/448835
Method and apparatus for generating generic descrambled data patterns for testing ECC protected memory May 29, 2003 Issued
Array ( [id] => 553494 [patent_doc_number] => 07174419 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-02-06 [patent_title] => 'Content addressable memory device with source-selecting data translator' [patent_app_type] => utility [patent_app_number] => 10/448819 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 18159 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/174/07174419.pdf [firstpage_image] =>[orig_patent_app_number] => 10448819 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/448819
Content addressable memory device with source-selecting data translator May 29, 2003 Issued
Array ( [id] => 7266455 [patent_doc_number] => 20040243783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Method and apparatus for multi-mode operation in a semiconductor circuit' [patent_app_type] => new [patent_app_number] => 10/448944 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5191 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20040243783.pdf [firstpage_image] =>[orig_patent_app_number] => 10448944 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/448944
Method and apparatus for multi-mode operation in a semiconductor circuit May 29, 2003 Abandoned
Array ( [id] => 404194 [patent_doc_number] => 07293155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-06 [patent_title] => 'Management of access to data from memory' [patent_app_type] => utility [patent_app_number] => 10/449316 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 11739 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/293/07293155.pdf [firstpage_image] =>[orig_patent_app_number] => 10449316 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/449316
Management of access to data from memory May 29, 2003 Issued
Array ( [id] => 7266420 [patent_doc_number] => 20040243769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Tree based memory structure' [patent_app_type] => new [patent_app_number] => 10/449216 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4469 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20040243769.pdf [firstpage_image] =>[orig_patent_app_number] => 10449216 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/449216
Tree based memory structure May 29, 2003 Abandoned
Array ( [id] => 156188 [patent_doc_number] => 07680990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-16 [patent_title] => 'Superword memory-access instructions for data processor' [patent_app_type] => utility [patent_app_number] => 10/449442 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3231 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/680/07680990.pdf [firstpage_image] =>[orig_patent_app_number] => 10449442 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/449442
Superword memory-access instructions for data processor May 29, 2003 Issued
Array ( [id] => 635830 [patent_doc_number] => 07130144 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-31 [patent_title] => 'Substrate structure of disk array apparatus, disk array apparatus and disk array system' [patent_app_type] => utility [patent_app_number] => 10/445490 [patent_app_country] => US [patent_app_date] => 2003-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4223 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/130/07130144.pdf [firstpage_image] =>[orig_patent_app_number] => 10445490 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/445490
Substrate structure of disk array apparatus, disk array apparatus and disk array system May 26, 2003 Issued
Array ( [id] => 6703082 [patent_doc_number] => 20030225962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'Memory card and memory card system' [patent_app_type] => new [patent_app_number] => 10/435594 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7462 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20030225962.pdf [firstpage_image] =>[orig_patent_app_number] => 10435594 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/435594
Memory card and memory card system May 11, 2003 Abandoned
Array ( [id] => 6822914 [patent_doc_number] => 20030221075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-27 [patent_title] => 'Computer system for managing data transfer between storage sub-systems' [patent_app_type] => new [patent_app_number] => 10/435260 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6305 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20030221075.pdf [firstpage_image] =>[orig_patent_app_number] => 10435260 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/435260
Computer system for managing data transfer between storage sub-systems May 11, 2003 Issued
Array ( [id] => 7436071 [patent_doc_number] => 20040230740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Cascading Content Addressable Memory Devices with Programmable Input / Output Connections' [patent_app_type] => new [patent_app_number] => 10/249842 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5768 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20040230740.pdf [firstpage_image] =>[orig_patent_app_number] => 10249842 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/249842
Cascading content addressable memory devices with programmable input/output connections May 11, 2003 Issued
Array ( [id] => 843585 [patent_doc_number] => 07392347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-24 [patent_title] => 'Systems and methods for buffering data between a coherency cache controller and memory' [patent_app_type] => utility [patent_app_number] => 10/435140 [patent_app_country] => US [patent_app_date] => 2003-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 5848 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/392/07392347.pdf [firstpage_image] =>[orig_patent_app_number] => 10435140 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/435140
Systems and methods for buffering data between a coherency cache controller and memory May 9, 2003 Issued
Array ( [id] => 6771175 [patent_doc_number] => 20030217115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-20 [patent_title] => 'Load-linked/store conditional mechanism in a CC-NUMA system' [patent_app_type] => new [patent_app_number] => 10/435189 [patent_app_country] => US [patent_app_date] => 2003-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 16637 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20030217115.pdf [firstpage_image] =>[orig_patent_app_number] => 10435189 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/435189
Load-linked/store conditional mechanism in a CC-NUMA system May 8, 2003 Issued
Array ( [id] => 305579 [patent_doc_number] => 07536509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Method for fetching data from a non-volatile memory in an integrated circuit and corresponding integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/512621 [patent_app_country] => US [patent_app_date] => 2003-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3704 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/536/07536509.pdf [firstpage_image] =>[orig_patent_app_number] => 10512621 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/512621
Method for fetching data from a non-volatile memory in an integrated circuit and corresponding integrated circuit Apr 28, 2003 Issued
Array ( [id] => 619721 [patent_doc_number] => 07146477 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-12-05 [patent_title] => 'Mechanism for selectively blocking peripheral device accesses to system memory' [patent_app_type] => utility [patent_app_number] => 10/419090 [patent_app_country] => US [patent_app_date] => 2003-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7441 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/146/07146477.pdf [firstpage_image] =>[orig_patent_app_number] => 10419090 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/419090
Mechanism for selectively blocking peripheral device accesses to system memory Apr 17, 2003 Issued
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