
Benjamin Lee Osterhout
Examiner (ID: 8550)
| Most Active Art Unit | 1711 |
| Art Unit(s) | 1711, 1792 |
| Total Applications | 1134 |
| Issued Applications | 889 |
| Pending Applications | 77 |
| Abandoned Applications | 198 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17558209
[patent_doc_number] => 11314918
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-04-26
[patent_title] => Method and apparatus for path routing
[patent_app_type] => utility
[patent_app_number] => 17/080161
[patent_app_country] => US
[patent_app_date] => 2020-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6057
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17080161
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/080161 | Method and apparatus for path routing | Oct 25, 2020 | Issued |
Array
(
[id] => 18873474
[patent_doc_number] => 11861285
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-02
[patent_title] => Electromigration evaluation methodology with consideration of current distribution
[patent_app_type] => utility
[patent_app_number] => 17/070579
[patent_app_country] => US
[patent_app_date] => 2020-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5819
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17070579
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/070579 | Electromigration evaluation methodology with consideration of current distribution | Oct 13, 2020 | Issued |
Array
(
[id] => 16624249
[patent_doc_number] => 20210042902
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-11
[patent_title] => REVERSE ENGINEERING DATA ANALYSIS SYSTEM, AND INTEGRATED CIRCUIT COMPONENT DATA PROCESSING TOOL AND METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/068590
[patent_app_country] => US
[patent_app_date] => 2020-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8924
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17068590
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/068590 | Reverse engineering data analysis system, and integrated circuit component data processing tool and method thereof | Oct 11, 2020 | Issued |
Array
(
[id] => 16730073
[patent_doc_number] => 20210097220
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-01
[patent_title] => SYSTEMS AND METHODS FOR MACHINE INTELLIGENCE BASED MALICIOUS DESIGN ALTERATION INSERTION
[patent_app_type] => utility
[patent_app_number] => 17/035959
[patent_app_country] => US
[patent_app_date] => 2020-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12200
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17035959
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/035959 | Systems and methods for machine intelligence based malicious design alteration insertion | Sep 28, 2020 | Issued |
Array
(
[id] => 17395083
[patent_doc_number] => 11244097
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-02-08
[patent_title] => System and method for determining hybrid-manufacturing process plans for printed circuit boards based on satisfiability modulo difference logic solver
[patent_app_type] => utility
[patent_app_number] => 17/023117
[patent_app_country] => US
[patent_app_date] => 2020-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 5449
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17023117
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/023117 | System and method for determining hybrid-manufacturing process plans for printed circuit boards based on satisfiability modulo difference logic solver | Sep 15, 2020 | Issued |
Array
(
[id] => 17528919
[patent_doc_number] => 11301608
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-04-12
[patent_title] => Layout-based side-channel emission analysis
[patent_app_type] => utility
[patent_app_number] => 16/948158
[patent_app_country] => US
[patent_app_date] => 2020-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 7110
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16948158
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/948158 | Layout-based side-channel emission analysis | Sep 3, 2020 | Issued |
Array
(
[id] => 18130465
[patent_doc_number] => 11556676
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-17
[patent_title] => Scalable formal security verification of circuit designs
[patent_app_type] => utility
[patent_app_number] => 17/011263
[patent_app_country] => US
[patent_app_date] => 2020-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 7145
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17011263
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/011263 | Scalable formal security verification of circuit designs | Sep 2, 2020 | Issued |
Array
(
[id] => 16516529
[patent_doc_number] => 20200395787
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-17
[patent_title] => WIRELESS POWER CONTROL METHOD AND DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/004397
[patent_app_country] => US
[patent_app_date] => 2020-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14599
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17004397
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/004397 | Wireless power control method and device | Aug 26, 2020 | Issued |
Array
(
[id] => 17325592
[patent_doc_number] => 11216606
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-01-04
[patent_title] => Method and system for functional safety verification using fault relation rules
[patent_app_type] => utility
[patent_app_number] => 16/942801
[patent_app_country] => US
[patent_app_date] => 2020-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5743
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 246
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16942801
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/942801 | Method and system for functional safety verification using fault relation rules | Jul 29, 2020 | Issued |
Array
(
[id] => 17851302
[patent_doc_number] => 20220281343
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-08
[patent_title] => CHARGING MANAGEMENT DEVICE, WIRELESS CHARGING SYSTEM, SERVER, AND METHOD FOR PROVIDING WIRELESS CHARGING SERVICES
[patent_app_type] => utility
[patent_app_number] => 17/631248
[patent_app_country] => US
[patent_app_date] => 2020-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14174
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17631248
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/631248 | Charging management device, wireless charging system, server, and method for providing wireless charging services | Jul 29, 2020 | Issued |
Array
(
[id] => 16601972
[patent_doc_number] => 20210028503
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-28
[patent_title] => DC-DC-CONVERTER-BASED ACTIVE VOLTAGE-BALANCING SYSTEM AND METHOD FOR PARALLEL BATTERY PACKS
[patent_app_type] => utility
[patent_app_number] => 16/930749
[patent_app_country] => US
[patent_app_date] => 2020-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8092
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16930749
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/930749 | DC-DC-converter-based active voltage-balancing system and method for parallel battery packs | Jul 15, 2020 | Issued |
Array
(
[id] => 16378427
[patent_doc_number] => 20200327269
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-15
[patent_title] => SYSTEM AND METHOD FOR SIMULATING AND ANALYZING QUANTUM CIRCUITS
[patent_app_type] => utility
[patent_app_number] => 16/913292
[patent_app_country] => US
[patent_app_date] => 2020-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6911
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16913292
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/913292 | System and method for simulating and analyzing quantum circuits | Jun 25, 2020 | Issued |
Array
(
[id] => 18750484
[patent_doc_number] => 11809798
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-11-07
[patent_title] => Implementing large multipliers in tensor arrays
[patent_app_type] => utility
[patent_app_number] => 16/914018
[patent_app_country] => US
[patent_app_date] => 2020-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 42
[patent_figures_cnt] => 43
[patent_no_of_words] => 17611
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16914018
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/914018 | Implementing large multipliers in tensor arrays | Jun 25, 2020 | Issued |
Array
(
[id] => 20595632
[patent_doc_number] => 12579351
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-03-17
[patent_title] => Programmatically generated reduced fault injections for functional safety circuits
[patent_app_type] => utility
[patent_app_number] => 17/999576
[patent_app_country] => US
[patent_app_date] => 2020-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4932
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17999576
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/999576 | Programmatically generated reduced fault injections for functional safety circuits | Jun 24, 2020 | Issued |
Array
(
[id] => 18890073
[patent_doc_number] => 11868846
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-01-09
[patent_title] => Quantum computing simulation using comparative rejection sampling
[patent_app_type] => utility
[patent_app_number] => 16/909938
[patent_app_country] => US
[patent_app_date] => 2020-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 19
[patent_no_of_words] => 16385
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16909938
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/909938 | Quantum computing simulation using comparative rejection sampling | Jun 22, 2020 | Issued |
Array
(
[id] => 17438041
[patent_doc_number] => 11263376
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-03-01
[patent_title] => System and method for fixing unknowns when simulating nested clock gaters
[patent_app_type] => utility
[patent_app_number] => 16/909963
[patent_app_country] => US
[patent_app_date] => 2020-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4182
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16909963
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/909963 | System and method for fixing unknowns when simulating nested clock gaters | Jun 22, 2020 | Issued |
Array
(
[id] => 16332976
[patent_doc_number] => 20200303942
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-24
[patent_title] => PORTABLE PROPANE-FUELED BATTERY CHARGER
[patent_app_type] => utility
[patent_app_number] => 16/897750
[patent_app_country] => US
[patent_app_date] => 2020-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5248
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16897750
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/897750 | Portable propane-fueled battery charger | Jun 9, 2020 | Issued |
Array
(
[id] => 16439388
[patent_doc_number] => 20200356714
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-11-12
[patent_title] => SYSTEMS AND METHODS FOR INTER-DIE BLOCK LEVEL DESIGN
[patent_app_type] => utility
[patent_app_number] => 16/882349
[patent_app_country] => US
[patent_app_date] => 2020-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3485
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882349
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/882349 | Systems and methods for inter-die block level design | May 21, 2020 | Issued |
Array
(
[id] => 17018906
[patent_doc_number] => 11088556
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-10
[patent_title] => Power system for high temperature applications with rechargeable energy storage
[patent_app_type] => utility
[patent_app_number] => 15/930069
[patent_app_country] => US
[patent_app_date] => 2020-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 28
[patent_no_of_words] => 23667
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15930069
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/930069 | Power system for high temperature applications with rechargeable energy storage | May 11, 2020 | Issued |
Array
(
[id] => 19078522
[patent_doc_number] => 11947890
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-02
[patent_title] => Implementation of deep neural networks for testing and quality control in the production of memory devices
[patent_app_type] => utility
[patent_app_number] => 16/870070
[patent_app_country] => US
[patent_app_date] => 2020-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 39
[patent_no_of_words] => 12244
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 250
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16870070
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/870070 | Implementation of deep neural networks for testing and quality control in the production of memory devices | May 7, 2020 | Issued |