Search

Benjamin Lee Osterhout

Examiner (ID: 8550)

Most Active Art Unit
1711
Art Unit(s)
1711, 1792
Total Applications
1134
Issued Applications
889
Pending Applications
77
Abandoned Applications
198

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15121493 [patent_doc_number] => 20190347380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => TIME-DRIVEN PLACEMENT AND/OR CLONING OF COMPONENTS FOR AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/520593 [patent_app_country] => US [patent_app_date] => 2019-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12559 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16520593 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/520593
Time-driven placement and/or cloning of components for an integrated circuit Jul 23, 2019 Issued
Array ( [id] => 16706703 [patent_doc_number] => 10956638 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-23 [patent_title] => Programmable integrated circuits for emulation [patent_app_type] => utility [patent_app_number] => 16/514324 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8793 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16514324 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/514324
Programmable integrated circuits for emulation Jul 16, 2019 Issued
Array ( [id] => 15043463 [patent_doc_number] => 20190332736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => INTEGRATED CIRCUIT DESIGNING SYSTEM [patent_app_type] => utility [patent_app_number] => 16/507763 [patent_app_country] => US [patent_app_date] => 2019-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6062 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16507763 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/507763
Integrated circuit designing system Jul 9, 2019 Issued
Array ( [id] => 16535558 [patent_doc_number] => 10878159 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-29 [patent_title] => Insertion and placement of pipeline registers in signal paths of an integrated circuit [patent_app_type] => utility [patent_app_number] => 16/503002 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 6121 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503002 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/503002
Insertion and placement of pipeline registers in signal paths of an integrated circuit Jul 2, 2019 Issued
Array ( [id] => 16566041 [patent_doc_number] => 10891410 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-01-12 [patent_title] => User-defined rule engine [patent_app_type] => utility [patent_app_number] => 16/503292 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 12475 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503292 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/503292
User-defined rule engine Jul 2, 2019 Issued
Array ( [id] => 15412987 [patent_doc_number] => 20200026816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => METHOD FOR OUTPUTTING IMPACT DEGREE AND INFORMATION PROCESSING DEVICE [patent_app_type] => utility [patent_app_number] => 16/502074 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10404 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16502074 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/502074
Method for outputting impact degree and information processing device Jul 2, 2019 Issued
Array ( [id] => 16698994 [patent_doc_number] => 10949597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => Through-silicon vias in integrated circuit packaging [patent_app_type] => utility [patent_app_number] => 16/460137 [patent_app_country] => US [patent_app_date] => 2019-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 8837 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16460137 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/460137
Through-silicon vias in integrated circuit packaging Jul 1, 2019 Issued
Array ( [id] => 15333311 [patent_doc_number] => 20200006985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => MODULE FOR INDUCTIVE ENERGY TRANSFER [patent_app_type] => utility [patent_app_number] => 16/453485 [patent_app_country] => US [patent_app_date] => 2019-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16453485 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/453485
Module for inductive energy transfer Jun 25, 2019 Issued
Array ( [id] => 17119300 [patent_doc_number] => 11130418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => Method and apparatus for aligning a vehicle with a wireless charging system [patent_app_type] => utility [patent_app_number] => 16/449627 [patent_app_country] => US [patent_app_date] => 2019-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5100 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16449627 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/449627
Method and apparatus for aligning a vehicle with a wireless charging system Jun 23, 2019 Issued
Array ( [id] => 18087704 [patent_doc_number] => 11537841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => System and method for compact neural network modeling of transistors [patent_app_type] => utility [patent_app_number] => 16/430219 [patent_app_country] => US [patent_app_date] => 2019-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8281 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16430219 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/430219
System and method for compact neural network modeling of transistors Jun 2, 2019 Issued
Array ( [id] => 16551613 [patent_doc_number] => 10884772 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-01-05 [patent_title] => Method and system for emulating an image processing system [patent_app_type] => utility [patent_app_number] => 16/427710 [patent_app_country] => US [patent_app_date] => 2019-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4021 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16427710 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/427710
Method and system for emulating an image processing system May 30, 2019 Issued
Array ( [id] => 16180966 [patent_doc_number] => 20200227935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => Wireless Power System [patent_app_type] => utility [patent_app_number] => 16/424331 [patent_app_country] => US [patent_app_date] => 2019-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16424331 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/424331
Wireless power system May 27, 2019 Issued
Array ( [id] => 17018759 [patent_doc_number] => 11088407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => System and method of managing battery cells [patent_app_type] => utility [patent_app_number] => 16/421718 [patent_app_country] => US [patent_app_date] => 2019-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 9830 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16421718 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/421718
System and method of managing battery cells May 23, 2019 Issued
Array ( [id] => 16608282 [patent_doc_number] => 10909289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Livelock detection in a hardware design using formal evaluation logic [patent_app_type] => utility [patent_app_number] => 16/419734 [patent_app_country] => US [patent_app_date] => 2019-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14141 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16419734 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/419734
Livelock detection in a hardware design using formal evaluation logic May 21, 2019 Issued
Array ( [id] => 15185953 [patent_doc_number] => 20190363568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => SOLAR WIRELESS COLLECTOR BEACON (DATA HUB) [patent_app_type] => utility [patent_app_number] => 16/420026 [patent_app_country] => US [patent_app_date] => 2019-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10910 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16420026 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/420026
Solar wireless collector beacon (data hub) May 21, 2019 Issued
Array ( [id] => 16332972 [patent_doc_number] => 20200303938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => PREDICTIVE MANAGEMENT OF BATTERY OPERATION [patent_app_type] => utility [patent_app_number] => 16/417330 [patent_app_country] => US [patent_app_date] => 2019-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16417330 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/417330
Predictive management of battery operation May 19, 2019 Issued
Array ( [id] => 14811479 [patent_doc_number] => 20190272349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-05 [patent_title] => Assessing Performance of a Hardware Design Using Formal Evaluation Logic [patent_app_type] => utility [patent_app_number] => 16/414594 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13591 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414594 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/414594
Assessing performance of a hardware design using formal evaluation logic May 15, 2019 Issued
Array ( [id] => 16201009 [patent_doc_number] => 10726176 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-28 [patent_title] => Method and apparatus for designing electrical and electronic circuits [patent_app_type] => utility [patent_app_number] => 16/412954 [patent_app_country] => US [patent_app_date] => 2019-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4868 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16412954 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/412954
Method and apparatus for designing electrical and electronic circuits May 14, 2019 Issued
Array ( [id] => 16338443 [patent_doc_number] => 10789403 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-29 [patent_title] => Grouping and partitioning of properties for logic verification [patent_app_type] => utility [patent_app_number] => 16/411193 [patent_app_country] => US [patent_app_date] => 2019-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7058 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16411193 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/411193
Grouping and partitioning of properties for logic verification May 13, 2019 Issued
Array ( [id] => 17955426 [patent_doc_number] => 11481535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Numerical information generation apparatus, numerical information generation method, and program [patent_app_type] => utility [patent_app_number] => 17/054653 [patent_app_country] => US [patent_app_date] => 2019-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 8612 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17054653 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/054653
Numerical information generation apparatus, numerical information generation method, and program May 13, 2019 Issued
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