Search

Benjamin Lee Osterhout

Examiner (ID: 8550)

Most Active Art Unit
1711
Art Unit(s)
1711, 1792
Total Applications
1134
Issued Applications
889
Pending Applications
77
Abandoned Applications
198

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13738719 [patent_doc_number] => 20180373829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => METHODS AND APPARATUS FOR REGULATING THE SUPPLY VOLTAGE OF AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/053714 [patent_app_country] => US [patent_app_date] => 2018-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9966 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16053714 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/053714
Methods and apparatus for regulating the supply voltage of an integrated circuit Aug 1, 2018 Issued
Array ( [id] => 15487841 [patent_doc_number] => 10559275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-11 [patent_title] => Inferring battery status of an electronic device in a wireless power delivery environment [patent_app_type] => utility [patent_app_number] => 16/049356 [patent_app_country] => US [patent_app_date] => 2018-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 12892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16049356 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/049356
Inferring battery status of an electronic device in a wireless power delivery environment Jul 29, 2018 Issued
Array ( [id] => 15412989 [patent_doc_number] => 20200026817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => COHERENT PLACEMENT OF SLOTLINE MODE SUPPRESSION STRUCTURES IN COPLANAR WAVEGUIDES FOR QUANTUM DEVICES [patent_app_type] => utility [patent_app_number] => 16/039597 [patent_app_country] => US [patent_app_date] => 2018-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8200 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16039597 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/039597
Coherent placement of slotline mode suppression structures in coplanar waveguides for quantum devices Jul 18, 2018 Issued
Array ( [id] => 15412983 [patent_doc_number] => 20200026814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => Timing-adaptive, configurable logic architecture [patent_app_type] => utility [patent_app_number] => 16/038207 [patent_app_country] => US [patent_app_date] => 2018-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16038207 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/038207
Timing-adaptive, configurable logic architecture Jul 17, 2018 Issued
Array ( [id] => 15789637 [patent_doc_number] => 10628545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Providing guidance to an equivalence checker when a design contains retimed registers [patent_app_type] => utility [patent_app_number] => 16/037936 [patent_app_country] => US [patent_app_date] => 2018-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3807 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16037936 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/037936
Providing guidance to an equivalence checker when a design contains retimed registers Jul 16, 2018 Issued
Array ( [id] => 15399607 [patent_doc_number] => 10540461 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-01-21 [patent_title] => Method and system for functional safety verification [patent_app_type] => utility [patent_app_number] => 16/038152 [patent_app_country] => US [patent_app_date] => 2018-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4582 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16038152 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/038152
Method and system for functional safety verification Jul 16, 2018 Issued
Array ( [id] => 13558639 [patent_doc_number] => 20180330867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => METHODS FOR FORMING SHIELD MATERIALS ONTO INDUCTIVE COILS [patent_app_type] => utility [patent_app_number] => 16/030493 [patent_app_country] => US [patent_app_date] => 2018-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6078 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16030493 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/030493
METHODS FOR FORMING SHIELD MATERIALS ONTO INDUCTIVE COILS Jul 8, 2018 Abandoned
Array ( [id] => 13797743 [patent_doc_number] => 20190012410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => OPTIMIZATION APPARATUS AND METHOD OF CONTROLLING OPTIMIZATION APPARATUS [patent_app_type] => utility [patent_app_number] => 16/021259 [patent_app_country] => US [patent_app_date] => 2018-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16021259 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/021259
Optimization apparatus and method of controlling optimization apparatus Jun 27, 2018 Issued
Array ( [id] => 15329177 [patent_doc_number] => 20200004918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => CLASSIFICATION AND LOCALIZATION OF HOTSPOTS IN INTEGRATED PHYSICAL DESIGN LAYOUTS [patent_app_type] => utility [patent_app_number] => 16/020417 [patent_app_country] => US [patent_app_date] => 2018-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6732 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16020417 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/020417
Classification and localization of hotspots in integrated physical design layouts Jun 26, 2018 Issued
Array ( [id] => 15639271 [patent_doc_number] => 10592629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Optimization apparatus and method of controlling the same [patent_app_type] => utility [patent_app_number] => 16/019866 [patent_app_country] => US [patent_app_date] => 2018-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9529 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16019866 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/019866
Optimization apparatus and method of controlling the same Jun 26, 2018 Issued
Array ( [id] => 15297907 [patent_doc_number] => 20190392089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => AUTOMATED REGION BASED OPTIMIZATION OF CHIP MANUFACTURE [patent_app_type] => utility [patent_app_number] => 16/017126 [patent_app_country] => US [patent_app_date] => 2018-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5167 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16017126 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/017126
Automated region based optimization of chip manufacture Jun 24, 2018 Issued
Array ( [id] => 15953309 [patent_doc_number] => 10664564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Systems and methods for inter-die block level design [patent_app_type] => utility [patent_app_number] => 16/016347 [patent_app_country] => US [patent_app_date] => 2018-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3485 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16016347 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/016347
Systems and methods for inter-die block level design Jun 21, 2018 Issued
Array ( [id] => 17394461 [patent_doc_number] => 11243473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Measurement method and apparatus [patent_app_type] => utility [patent_app_number] => 16/615207 [patent_app_country] => US [patent_app_date] => 2018-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 17195 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16615207 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/615207
Measurement method and apparatus May 27, 2018 Issued
Array ( [id] => 13581839 [patent_doc_number] => 20180342468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => Defense Techniques for Split Manufacturing [patent_app_type] => utility [patent_app_number] => 15/987309 [patent_app_country] => US [patent_app_date] => 2018-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11749 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15987309 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/987309
Defense techniques for split manufacturing May 22, 2018 Issued
Array ( [id] => 15669643 [patent_doc_number] => 10599046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-24 [patent_title] => Method, a non-transitory computer-readable medium, and/or an apparatus for determining whether to order a mask structure [patent_app_type] => utility [patent_app_number] => 15/987238 [patent_app_country] => US [patent_app_date] => 2018-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 10756 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15987238 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/987238
Method, a non-transitory computer-readable medium, and/or an apparatus for determining whether to order a mask structure May 22, 2018 Issued
Array ( [id] => 15936693 [patent_doc_number] => 20200159980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => Method for a computer-aided automated verification of requirements [patent_app_type] => utility [patent_app_number] => 16/611234 [patent_app_country] => US [patent_app_date] => 2018-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6134 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16611234 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/611234
Method for a computer-aided automated verification of requirements May 7, 2018 Abandoned
Array ( [id] => 16187448 [patent_doc_number] => 10720792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-21 [patent_title] => Portable propane-fueled battery charger [patent_app_type] => utility [patent_app_number] => 15/970405 [patent_app_country] => US [patent_app_date] => 2018-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5062 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15970405 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/970405
Portable propane-fueled battery charger May 2, 2018 Issued
Array ( [id] => 15564097 [patent_doc_number] => 20200066460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => SUPERCAPACITOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/609753 [patent_app_country] => US [patent_app_date] => 2018-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2772 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16609753 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/609753
SUPERCAPACITOR DEVICE May 1, 2018 Abandoned
Array ( [id] => 13556635 [patent_doc_number] => 20180329865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => DYNAMIC OUTLIER BIAS REDUCTION SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 15/963817 [patent_app_country] => US [patent_app_date] => 2018-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11734 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 555 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15963817 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/963817
Dynamic outlier bias reduction system and method Apr 25, 2018 Issued
Array ( [id] => 14980737 [patent_doc_number] => 10444276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => Computing device executing program performing method of analyzing power noise in semiconductor device, semiconductor device design method, and program storage medium storing program [patent_app_type] => utility [patent_app_number] => 15/949114 [patent_app_country] => US [patent_app_date] => 2018-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6374 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15949114 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/949114
Computing device executing program performing method of analyzing power noise in semiconductor device, semiconductor device design method, and program storage medium storing program Apr 9, 2018 Issued
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