Benjamin Lee Osterhout

Array ( [id] => 17423378 [patent_doc_number] => 11256836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Toggle rate reduction in high level programming implementations [patent_app_type] => utility [patent_app_number] => 15/842311 [patent_app_country] => US [patent_app_date] => 2017-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 8381 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15842311 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15313787 [patent_doc_number] => 10521600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Reconfigurable system-on-chip security architecture [patent_app_type] => utility [patent_app_number] => 15/840509 [patent_app_country] => US [patent_app_date] => 2017-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 9537 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15840509 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12262813 [patent_doc_number] => 20180082009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'PROCESS FOR IMPROVING CAPACITANCE EXTRACTION PERFORMANCE' [patent_app_type] => utility [patent_app_number] => 15/832249 [patent_app_country] => US [patent_app_date] => 2017-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4674 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15832249 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15642281 [patent_doc_number] => 10594155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => System and method for powering or charging small-volume or small-surface receivers or devices [patent_app_type] => utility [patent_app_number] => 15/830411 [patent_app_country] => US [patent_app_date] => 2017-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 13890 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15830411 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15285007 [patent_doc_number] => 10515168 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-24 [patent_title] => Formal verification using microtransactions [patent_app_type] => utility [patent_app_number] => 15/809892 [patent_app_country] => US [patent_app_date] => 2017-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 23079 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15809892 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14939929 [patent_doc_number] => 20190305603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => METHOD FOR DESIGNING SIGNAL WAVEFORMS [patent_app_type] => utility [patent_app_number] => 16/346527 [patent_app_country] => US [patent_app_date] => 2017-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5358 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16346527 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13318909 [patent_doc_number] => 20180210992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => METHOD FOR EFFICIENT LOCALIZED SELF-HEATING ANALYSIS USING LOCATION BASED DELTAT ANALYSIS [patent_app_type] => utility [patent_app_number] => 15/792820 [patent_app_country] => US [patent_app_date] => 2017-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7225 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15792820 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17062177 [patent_doc_number] => 11106782 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-31 [patent_title] => Control unit for a battery system [patent_app_type] => utility [patent_app_number] => 16/343220 [patent_app_country] => US [patent_app_date] => 2017-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 11633 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16343220 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12695146 [patent_doc_number] => 20180123548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => SIGNAL CHANNEL FOR REDUCING CROSSTALK NOISE, MODULE SUBSTRATE AND MEMORY MODULE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 15/720326 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9281 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15720326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14138201 [patent_doc_number] => 20190103490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => DUAL GATE METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR [patent_app_type] => utility [patent_app_number] => 15/720977 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5834 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -39 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15720977 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14136233 [patent_doc_number] => 20190102506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => SEMICONDUCTOR PACKAGE METAL SHADOWING CHECKS [patent_app_type] => utility [patent_app_number] => 15/719743 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8655 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15719743 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14136231 [patent_doc_number] => 20190102505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => SEMICONDUCTOR PACKAGE FLOATING METAL CHECKS [patent_app_type] => utility [patent_app_number] => 15/719698 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9672 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15719698 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14734659 [patent_doc_number] => 10386726 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Geometry vectorization for mask process correction [patent_app_type] => utility [patent_app_number] => 15/720182 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9639 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15720182 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16444731 [patent_doc_number] => 10836642 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Graphene semiconductor design method [patent_app_type] => utility [patent_app_number] => 16/476963 [patent_app_country] => US [patent_app_date] => 2017-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1894 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16476963 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13993251 [patent_doc_number] => 20190065783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => COMPUTATIONALLY IMPLEMENTED METHOD WITH ENABLED LOCKDOWN CODE AND CAPABILITY [patent_app_type] => utility [patent_app_number] => 15/690285 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4050 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690285 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13992985 [patent_doc_number] => 20190065650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => INTEGRATED CIRCUIT DESIGN AND/OR FABRICATION [patent_app_type] => utility [patent_app_number] => 15/690603 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9743 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690603 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12629412 [patent_doc_number] => 20180101634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => DESIGN ASSISTANCE PROGRAMS, DESIGN ASSISTANCE METHODS, AND INFORMATION PROCESSING APPARATUSES [patent_app_type] => utility [patent_app_number] => 15/690491 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690491 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14427775 [patent_doc_number] => 10318693 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-11 [patent_title] => Balanced scaled-load clustering [patent_app_type] => utility [patent_app_number] => 15/690043 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6103 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690043 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14857291 [patent_doc_number] => 10417375 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Time-driven placement and/or cloning of components for an integrated circuit [patent_app_type] => utility [patent_app_number] => 15/689791 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12559 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15689791 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16306920 [patent_doc_number] => 10775705 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Patterning stack optimization [patent_app_type] => utility [patent_app_number] => 16/325228 [patent_app_country] => US [patent_app_date] => 2017-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 24046 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16325228 [rel_patent_id] =>[rel_patent_doc_number] =>)