Search

Benjamin Lee Osterhout

Examiner (ID: 8550)

Most Active Art Unit
1711
Art Unit(s)
1711, 1792
Total Applications
1134
Issued Applications
889
Pending Applications
77
Abandoned Applications
198

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12187807 [patent_doc_number] => 20180046744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'SYSTEMS AND METHODS FOR CELL ABUTMENT' [patent_app_type] => utility [patent_app_number] => 15/334918 [patent_app_country] => US [patent_app_date] => 2016-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4980 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15334918 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/334918
Systems and methods for cell abutment Oct 25, 2016 Issued
Array ( [id] => 13292115 [patent_doc_number] => 10157253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => Multi-bit-mapping aware clock gating [patent_app_type] => utility [patent_app_number] => 15/295840 [patent_app_country] => US [patent_app_date] => 2016-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 25 [patent_no_of_words] => 8847 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15295840 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/295840
Multi-bit-mapping aware clock gating Oct 16, 2016 Issued
Array ( [id] => 13186495 [patent_doc_number] => 10108769 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-23 [patent_title] => Delay modeling for high fan-out nets within circuit designs [patent_app_type] => utility [patent_app_number] => 15/295911 [patent_app_country] => US [patent_app_date] => 2016-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 10072 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15295911 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/295911
Delay modeling for high fan-out nets within circuit designs Oct 16, 2016 Issued
Array ( [id] => 14669925 [patent_doc_number] => 10372864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Global routing in circuit design [patent_app_type] => utility [patent_app_number] => 15/293512 [patent_app_country] => US [patent_app_date] => 2016-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3965 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15293512 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/293512
Global routing in circuit design Oct 13, 2016 Issued
Array ( [id] => 13665513 [patent_doc_number] => 10162920 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-25 [patent_title] => System and method for performing out of order name resolution in an electronic design [patent_app_type] => utility [patent_app_number] => 15/294168 [patent_app_country] => US [patent_app_date] => 2016-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15294168 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/294168
System and method for performing out of order name resolution in an electronic design Oct 13, 2016 Issued
Array ( [id] => 13097413 [patent_doc_number] => 10068047 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-09-04 [patent_title] => Systems and methods for designing an integrated circuit [patent_app_type] => utility [patent_app_number] => 15/293725 [patent_app_country] => US [patent_app_date] => 2016-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7307 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15293725 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/293725
Systems and methods for designing an integrated circuit Oct 13, 2016 Issued
Array ( [id] => 13819339 [patent_doc_number] => 10186443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-22 [patent_title] => Misalignment/alignment compensation method, semiconductor lithography system, and method of semiconductor patterning [patent_app_type] => utility [patent_app_number] => 15/281083 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4817 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15281083 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/281083
Misalignment/alignment compensation method, semiconductor lithography system, and method of semiconductor patterning Sep 29, 2016 Issued
Array ( [id] => 11847472 [patent_doc_number] => 09735029 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-15 [patent_title] => 'Metal fill optimization for self-aligned double patterning' [patent_app_type] => utility [patent_app_number] => 15/273092 [patent_app_country] => US [patent_app_date] => 2016-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9433 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15273092 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/273092
Metal fill optimization for self-aligned double patterning Sep 21, 2016 Issued
Array ( [id] => 11385084 [patent_doc_number] => 20170011140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'METHOD AND APPARATUS FOR WORD-LEVEL NETLIST PREPROCESSING AND ANALYSIS USING SAME' [patent_app_type] => utility [patent_app_number] => 15/270958 [patent_app_country] => US [patent_app_date] => 2016-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8067 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15270958 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/270958
Method and apparatus for word-level netlist preprocessing and analysis using same Sep 19, 2016 Issued
Array ( [id] => 15639275 [patent_doc_number] => 10592631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Method for performing netlist comparison based on pin connection relationship of components [patent_app_type] => utility [patent_app_number] => 15/778156 [patent_app_country] => US [patent_app_date] => 2016-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3387 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15778156 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/778156
Method for performing netlist comparison based on pin connection relationship of components Aug 25, 2016 Issued
Array ( [id] => 12180787 [patent_doc_number] => 20180039723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'METHOD OF ADJUSTING METAL LINE PITCH' [patent_app_type] => utility [patent_app_number] => 15/229536 [patent_app_country] => US [patent_app_date] => 2016-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5529 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15229536 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/229536
Method of adjusting metal line pitch Aug 4, 2016 Issued
Array ( [id] => 11965316 [patent_doc_number] => 20170269470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'EFFICIENT WAY TO CREATING PROCESS WINDOW ENHANCED PHOTOMASK LAYOUT' [patent_app_type] => utility [patent_app_number] => 15/230356 [patent_app_country] => US [patent_app_date] => 2016-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5631 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15230356 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/230356
Efficient way to creating process window enhanced photomask layout Aug 4, 2016 Issued
Array ( [id] => 13241277 [patent_doc_number] => 10133839 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-20 [patent_title] => Systems and methods for estimating a power consumption of a register-transfer level circuit design [patent_app_type] => utility [patent_app_number] => 15/227512 [patent_app_country] => US [patent_app_date] => 2016-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 9327 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15227512 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/227512
Systems and methods for estimating a power consumption of a register-transfer level circuit design Aug 2, 2016 Issued
Array ( [id] => 11438287 [patent_doc_number] => 20170039308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-09 [patent_title] => 'Pre-Silicon Design Rule Evaluation' [patent_app_type] => utility [patent_app_number] => 15/227863 [patent_app_country] => US [patent_app_date] => 2016-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10416 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15227863 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/227863
Pre-silicon design rule evaluation Aug 2, 2016 Issued
Array ( [id] => 14286375 [patent_doc_number] => 20190140472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => CHARGING MINIATURE DEVICES [patent_app_type] => utility [patent_app_number] => 16/307331 [patent_app_country] => US [patent_app_date] => 2016-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7031 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16307331 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/307331
Charging miniature devices Jun 30, 2016 Issued
Array ( [id] => 13144197 [patent_doc_number] => 10089433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Method for triple-patterning friendly placement [patent_app_type] => utility [patent_app_number] => 15/145455 [patent_app_country] => US [patent_app_date] => 2016-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5255 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15145455 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/145455
Method for triple-patterning friendly placement May 2, 2016 Issued
Array ( [id] => 12032945 [patent_doc_number] => 20170323044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'SCALABLE LOGIC VERIFICATION BY IDENTIFYING UNATE PRIMARY INPUTS' [patent_app_type] => utility [patent_app_number] => 15/145543 [patent_app_country] => US [patent_app_date] => 2016-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8470 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15145543 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/145543
Scalable logic verification by identifying unate primary inputs May 2, 2016 Issued
Array ( [id] => 14736413 [patent_doc_number] => 10387606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Validating a clock tree delay [patent_app_type] => utility [patent_app_number] => 15/145741 [patent_app_country] => US [patent_app_date] => 2016-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 10369 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15145741 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/145741
Validating a clock tree delay May 2, 2016 Issued
Array ( [id] => 14394185 [patent_doc_number] => 10310371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Method and system for lithography process-window-maximizing optical proximity correction [patent_app_type] => utility [patent_app_number] => 15/144242 [patent_app_country] => US [patent_app_date] => 2016-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 29931 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15144242 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/144242
Method and system for lithography process-window-maximizing optical proximity correction May 1, 2016 Issued
Array ( [id] => 14458161 [patent_doc_number] => 10325044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Control path verification of hardware design for pipelined process [patent_app_type] => utility [patent_app_number] => 15/143772 [patent_app_country] => US [patent_app_date] => 2016-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12314 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15143772 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/143772
Control path verification of hardware design for pipelined process May 1, 2016 Issued
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