Search

Benjamin Lee Osterhout

Examiner (ID: 8550)

Most Active Art Unit
1711
Art Unit(s)
1711, 1792
Total Applications
1134
Issued Applications
889
Pending Applications
77
Abandoned Applications
198

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18795293 [patent_doc_number] => 11829066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Sub-resolution assist features [patent_app_type] => utility [patent_app_number] => 17/240265 [patent_app_country] => US [patent_app_date] => 2021-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17240265 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/240265
Sub-resolution assist features Apr 25, 2021 Issued
Array ( [id] => 18430728 [patent_doc_number] => 11675950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Method and apparatus for electromigration evaluation [patent_app_type] => utility [patent_app_number] => 17/235790 [patent_app_country] => US [patent_app_date] => 2021-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 9018 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17235790 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/235790
Method and apparatus for electromigration evaluation Apr 19, 2021 Issued
Array ( [id] => 17794493 [patent_doc_number] => 20220253585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => EXCITATION SOURCE PLANNING METHOD FOR ELECTRICAL SIMULATION AND SYSTEM THEREOF [patent_app_type] => utility [patent_app_number] => 17/231022 [patent_app_country] => US [patent_app_date] => 2021-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17231022 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/231022
Excitation source planning method for electrical simulation and system thereof Apr 14, 2021 Issued
Array ( [id] => 16994327 [patent_doc_number] => 20210232747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => Method and Structure for Mandrel and Spacer Patterning [patent_app_type] => utility [patent_app_number] => 17/229736 [patent_app_country] => US [patent_app_date] => 2021-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17229736 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/229736
Method and structure for mandrel and spacer patterning Apr 12, 2021 Issued
Array ( [id] => 18532288 [patent_doc_number] => 20230237361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => SYSTEM AND METHOD FOR GENERATING QUANTUM CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/919038 [patent_app_country] => US [patent_app_date] => 2021-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17293 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17919038 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/919038
SYSTEM AND METHOD FOR GENERATING QUANTUM CIRCUITS Apr 11, 2021 Pending
Array ( [id] => 17159457 [patent_doc_number] => 20210320508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => INDUCTIVE ELECTRONIC IDENTIFICATION DEVICE AND POWER SUPPLY COMPENSATION CIRCUIT OF THE SAME [patent_app_type] => utility [patent_app_number] => 17/223475 [patent_app_country] => US [patent_app_date] => 2021-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2977 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17223475 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/223475
Inductive electronic identification device and power-supply-compensation circuit of the same Apr 5, 2021 Issued
Array ( [id] => 17172835 [patent_doc_number] => 20210326505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => PATTERN CENTRIC PROCESS CONTROL [patent_app_type] => utility [patent_app_number] => 17/222132 [patent_app_country] => US [patent_app_date] => 2021-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23961 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17222132 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/222132
Pattern centric process control Apr 4, 2021 Issued
Array ( [id] => 20213097 [patent_doc_number] => 12409734 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Insulation fault response method and apparatus for fuel cell vehicle [patent_app_type] => utility [patent_app_number] => 17/758127 [patent_app_country] => US [patent_app_date] => 2021-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2659 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17758127 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/758127
Insulation fault response method and apparatus for fuel cell vehicle Mar 31, 2021 Issued
Array ( [id] => 18506645 [patent_doc_number] => 11704463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Method of etch model calibration using optical scatterometry [patent_app_type] => utility [patent_app_number] => 17/301345 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 18605 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17301345 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/301345
Method of etch model calibration using optical scatterometry Mar 30, 2021 Issued
Array ( [id] => 17128567 [patent_doc_number] => 20210303336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => Advanced Register Merging [patent_app_type] => utility [patent_app_number] => 17/217110 [patent_app_country] => US [patent_app_date] => 2021-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12010 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17217110 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/217110
Advanced register merging Mar 29, 2021 Issued
Array ( [id] => 20482044 [patent_doc_number] => 12530519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Electrical circuit design inspection system and method [patent_app_type] => utility [patent_app_number] => 17/906832 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3204 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17906832 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/906832
Electrical circuit design inspection system and method Mar 24, 2021 Issued
Array ( [id] => 20703463 [patent_doc_number] => 12626176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-12 [patent_title] => Systems and methods for scalable quantum computing [patent_app_type] => utility [patent_app_number] => 17/913548 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2201 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17913548 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/913548
SYSTEMS AND METHODS FOR SCALABLE QUANTUM COMPUTING Mar 24, 2021 Issued
Array ( [id] => 18031032 [patent_doc_number] => 11514222 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-29 [patent_title] => Cell-width aware buffer insertion technique for narrow channels [patent_app_type] => utility [patent_app_number] => 17/207266 [patent_app_country] => US [patent_app_date] => 2021-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5822 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17207266 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/207266
Cell-width aware buffer insertion technique for narrow channels Mar 18, 2021 Issued
Array ( [id] => 18047004 [patent_doc_number] => 11520960 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-06 [patent_title] => Register transfer level based side channel leakage assessment [patent_app_type] => utility [patent_app_number] => 17/201939 [patent_app_country] => US [patent_app_date] => 2021-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6291 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17201939 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/201939
Register transfer level based side channel leakage assessment Mar 14, 2021 Issued
Array ( [id] => 16994324 [patent_doc_number] => 20210232744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => LOGIC DRIVE BASED ON STANDARD COMMODITY FPGA IC CHIPS [patent_app_type] => utility [patent_app_number] => 17/187766 [patent_app_country] => US [patent_app_date] => 2021-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 191657 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187766 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/187766
Logic drive based on standard commodity FPGA IC chips Feb 26, 2021 Issued
Array ( [id] => 18072965 [patent_doc_number] => 11531799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Assessing performance of a hardware design using formal evaluation logic [patent_app_type] => utility [patent_app_number] => 17/184186 [patent_app_country] => US [patent_app_date] => 2021-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13604 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/184186
Assessing performance of a hardware design using formal evaluation logic Feb 23, 2021 Issued
Array ( [id] => 17977683 [patent_doc_number] => 11494545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Apparatus and method for advanced macro clock skewing [patent_app_type] => utility [patent_app_number] => 17/184184 [patent_app_country] => US [patent_app_date] => 2021-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5296 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184184 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/184184
Apparatus and method for advanced macro clock skewing Feb 23, 2021 Issued
Array ( [id] => 16887801 [patent_doc_number] => 20210173998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => Through-Silicon Vias in Integrated Circuit Packaging [patent_app_type] => utility [patent_app_number] => 17/179904 [patent_app_country] => US [patent_app_date] => 2021-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8867 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17179904 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/179904
Through-silicon vias in integrated circuit packaging Feb 18, 2021 Issued
Array ( [id] => 18415124 [patent_doc_number] => 11669667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Automatic test pattern generation (ATPG) for parametric faults [patent_app_type] => utility [patent_app_number] => 17/180013 [patent_app_country] => US [patent_app_date] => 2021-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6273 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17180013 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/180013
Automatic test pattern generation (ATPG) for parametric faults Feb 18, 2021 Issued
Array ( [id] => 16887793 [patent_doc_number] => 20210173990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => OPTIMIZATION DEVICE AND METHOD OF CONTROLLING OPTIMIZATION DEVICE [patent_app_type] => utility [patent_app_number] => 17/178290 [patent_app_country] => US [patent_app_date] => 2021-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16684 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17178290 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/178290
Optimization device and method of controlling optimization device Feb 17, 2021 Issued
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