| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3439285
[patent_doc_number] => 05455935
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-10-03
[patent_title] => 'Clock synchronization system'
[patent_app_type] => 1
[patent_app_number] => 8/219152
[patent_app_country] => US
[patent_app_date] => 1994-03-29
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/455/05455935.pdf
[firstpage_image] =>[orig_patent_app_number] => 219152
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/219152 | Clock synchronization system | Mar 28, 1994 | Issued |
| 08/218912 | DUAL MOTHERBOARD COMPUTER SYSTEM | Mar 24, 1994 | Abandoned |
Array
(
[id] => 3548871
[patent_doc_number] => 05495579
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-27
[patent_title] => 'Central processor with duplicate basic processing units employing multiplexed cache store control signals to reduce inter-unit conductor count'
[patent_app_type] => 1
[patent_app_number] => 8/218532
[patent_app_country] => US
[patent_app_date] => 1994-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/05/495/05495579.pdf
[firstpage_image] =>[orig_patent_app_number] => 218532
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/218532 | Central processor with duplicate basic processing units employing multiplexed cache store control signals to reduce inter-unit conductor count | Mar 24, 1994 | Issued |
| 08/218412 | METHOD TO PREVENT DATA LOSS IN AN ELECTRICALLY ERASABLE READ ONLY MEMORY | Mar 24, 1994 | Abandoned |
| 08/217572 | DIAGNOSTIC PROTOCOL AND DISPLAY SYSTEM | Mar 23, 1994 | Abandoned |
| 08/216262 | EFFICIENT DIRECT CELL REPLACEMENT FAULT TOLERANT ARCHITECTURE SUPPORTING COMPLETELY INTEGRATED SYSTEMS WITH MEANS FOR DIRECT COMMUNICATION WITH SYSTEM OPERATOR | Mar 21, 1994 | Abandoned |
Array
(
[id] => 3609762
[patent_doc_number] => 05559813
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-24
[patent_title] => 'Digital data processing system for transmitting information groups divided into segments comprised of video data, edc\'s, ecc\'s and sync data'
[patent_app_type] => 1
[patent_app_number] => 8/213478
[patent_app_country] => US
[patent_app_date] => 1994-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 1708
[patent_no_of_claims] => 19
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/559/05559813.pdf
[firstpage_image] =>[orig_patent_app_number] => 213478
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/213478 | Digital data processing system for transmitting information groups divided into segments comprised of video data, edc's, ecc's and sync data | Mar 15, 1994 | Issued |
Array
(
[id] => 3439272
[patent_doc_number] => 05455934
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-10-03
[patent_title] => 'Fault tolerant hard disk array controller'
[patent_app_type] => 1
[patent_app_number] => 8/212494
[patent_app_country] => US
[patent_app_date] => 1994-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[pdf_file] => patents/05/455/05455934.pdf
[firstpage_image] =>[orig_patent_app_number] => 212494
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/212494 | Fault tolerant hard disk array controller | Mar 10, 1994 | Issued |
Array
(
[id] => 3783888
[patent_doc_number] => 05734816
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-31
[patent_title] => 'Nonvolatile memory with flash erase capability'
[patent_app_type] => 1
[patent_app_number] => 8/212469
[patent_app_country] => US
[patent_app_date] => 1994-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
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[patent_no_of_words] => 6947
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[pdf_file] => patents/05/734/05734816.pdf
[firstpage_image] =>[orig_patent_app_number] => 212469
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/212469 | Nonvolatile memory with flash erase capability | Mar 9, 1994 | Issued |
Array
(
[id] => 3524130
[patent_doc_number] => 05513188
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-30
[patent_title] => 'Enhanced interconnect testing through utilization of board topology data'
[patent_app_type] => 1
[patent_app_number] => 8/208245
[patent_app_country] => US
[patent_app_date] => 1994-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/513/05513188.pdf
[firstpage_image] =>[orig_patent_app_number] => 208245
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/208245 | Enhanced interconnect testing through utilization of board topology data | Mar 8, 1994 | Issued |
| 08/206924 | MULTIPLE BUS CONTROL METHOD AND A SYSTEM THEREOF | Mar 6, 1994 | Abandoned |
Array
(
[id] => 3433692
[patent_doc_number] => 05422896
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-06-06
[patent_title] => 'Timing check circuit for a functional macro'
[patent_app_type] => 1
[patent_app_number] => 8/200000
[patent_app_country] => US
[patent_app_date] => 1994-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 5086
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/422/05422896.pdf
[firstpage_image] =>[orig_patent_app_number] => 200000
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/200000 | Timing check circuit for a functional macro | Feb 21, 1994 | Issued |
| 08/198132 | INTERFACE PROTOCOL FOR TESTING OF A CACHE MEMORY | Feb 15, 1994 | Abandoned |
| 08/193292 | METHOD AND APPARATUS FOR TESTING THE FUNCTIONALITY OF A MICROPROCESSOR | Feb 7, 1994 | Abandoned |
Array
(
[id] => 3561983
[patent_doc_number] => 05548718
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-20
[patent_title] => 'Method and system for determining software reliability'
[patent_app_type] => 1
[patent_app_number] => 8/178930
[patent_app_country] => US
[patent_app_date] => 1994-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => patents/05/548/05548718.pdf
[firstpage_image] =>[orig_patent_app_number] => 178930
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/178930 | Method and system for determining software reliability | Jan 6, 1994 | Issued |
Array
(
[id] => 3495321
[patent_doc_number] => 05446874
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-29
[patent_title] => 'Automated benchmarking with self customization'
[patent_app_type] => 1
[patent_app_number] => 8/173530
[patent_app_country] => US
[patent_app_date] => 1993-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 28
[patent_no_of_words] => 13999
[patent_no_of_claims] => 23
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[pdf_file] => patents/05/446/05446874.pdf
[firstpage_image] =>[orig_patent_app_number] => 173530
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/173530 | Automated benchmarking with self customization | Dec 22, 1993 | Issued |
| 08/171403 | METHOD AND APPARATUS FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES | Dec 21, 1993 | Abandoned |
Array
(
[id] => 3127929
[patent_doc_number] => 05396620
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-03-07
[patent_title] => 'Method for writing specific values last into data storage groups containing redundancy'
[patent_app_type] => 1
[patent_app_number] => 8/171113
[patent_app_country] => US
[patent_app_date] => 1993-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/396/05396620.pdf
[firstpage_image] =>[orig_patent_app_number] => 171113
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/171113 | Method for writing specific values last into data storage groups containing redundancy | Dec 20, 1993 | Issued |
Array
(
[id] => 3015957
[patent_doc_number] => 05371884
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-12-06
[patent_title] => 'Processor fault recovery system'
[patent_app_type] => 1
[patent_app_number] => 8/171600
[patent_app_country] => US
[patent_app_date] => 1993-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
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[pdf_file] => patents/05/371/05371884.pdf
[firstpage_image] =>[orig_patent_app_number] => 171600
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/171600 | Processor fault recovery system | Dec 20, 1993 | Issued |
| 08/169549 | UNINTERRUPTIBLE POWER SUPPLY | Dec 19, 1993 | Abandoned |
