Application number | Title of the application | Filing Date | Status |
---|
Array
(
[id] => 3083290
[patent_doc_number] => 05337322
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-08-09
[patent_title] => 'Method of processing stored data containing parity data'
[patent_app_type] => 1
[patent_app_number] => 7/844788
[patent_app_country] => US
[patent_app_date] => 1992-03-02
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/337/05337322.pdf
[firstpage_image] =>[orig_patent_app_number] => 844788
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/844788 | Method of processing stored data containing parity data | Mar 1, 1992 | Issued |
07/842672 | METHOD AND SYSTEM FOR SCREENING LOGIC CIRCUITS | Feb 26, 1992 | Abandoned |
Array
(
[id] => 3104498
[patent_doc_number] => 05313471
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-17
[patent_title] => 'Error concealing method'
[patent_app_type] => 1
[patent_app_number] => 7/840756
[patent_app_country] => US
[patent_app_date] => 1992-02-24
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/313/05313471.pdf
[firstpage_image] =>[orig_patent_app_number] => 840756
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/840756 | Error concealing method | Feb 23, 1992 | Issued |
07/830654 | WORK FLOW MANAGEMENT SYSTEM AND METHOD | Feb 3, 1992 | Abandoned |
Array
(
[id] => 3083179
[patent_doc_number] => 05337316
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-08-09
[patent_title] => 'Transceiver self-diagnostic testing apparatus and method'
[patent_app_type] => 1
[patent_app_number] => 7/829802
[patent_app_country] => US
[patent_app_date] => 1992-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/05/337/05337316.pdf
[firstpage_image] =>[orig_patent_app_number] => 829802
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/829802 | Transceiver self-diagnostic testing apparatus and method | Jan 30, 1992 | Issued |
Array
(
[id] => 3067312
[patent_doc_number] => 05357520
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-10-18
[patent_title] => 'Method and apparatus for precompensation value determination in a PRML data channel'
[patent_app_type] => 1
[patent_app_number] => 7/830032
[patent_app_country] => US
[patent_app_date] => 1992-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 2499
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[pdf_file] => patents/05/357/05357520.pdf
[firstpage_image] =>[orig_patent_app_number] => 830032
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/830032 | Method and apparatus for precompensation value determination in a PRML data channel | Jan 30, 1992 | Issued |
Array
(
[id] => 3021273
[patent_doc_number] => 05276690
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-04
[patent_title] => 'Apparatus utilizing dual compare logic for self checking of functional redundancy check (FRC) logic'
[patent_app_type] => 1
[patent_app_number] => 7/830209
[patent_app_country] => US
[patent_app_date] => 1992-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3729
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/276/05276690.pdf
[firstpage_image] =>[orig_patent_app_number] => 830209
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/830209 | Apparatus utilizing dual compare logic for self checking of functional redundancy check (FRC) logic | Jan 29, 1992 | Issued |
07/827165 | AUTOMATIC EQUALIZER | Jan 27, 1992 | Abandoned |
Array
(
[id] => 3024344
[patent_doc_number] => 05333306
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-07-26
[patent_title] => 'Information processing system having a data protection unit'
[patent_app_type] => 1
[patent_app_number] => 7/826805
[patent_app_country] => US
[patent_app_date] => 1992-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 2801
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[pdf_file] => patents/05/333/05333306.pdf
[firstpage_image] =>[orig_patent_app_number] => 826805
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/826805 | Information processing system having a data protection unit | Jan 27, 1992 | Issued |
Array
(
[id] => 3091374
[patent_doc_number] => 05321698
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-06-14
[patent_title] => 'Method and apparatus for providing retry coverage in multi-process computer environment'
[patent_app_type] => 1
[patent_app_number] => 7/815320
[patent_app_country] => US
[patent_app_date] => 1991-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 13410
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/321/05321698.pdf
[firstpage_image] =>[orig_patent_app_number] => 815320
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/815320 | Method and apparatus for providing retry coverage in multi-process computer environment | Dec 26, 1991 | Issued |
07/811205 | CLOCKING MECHANISM FOR DELAY, SHORT PATH AND STUCK-AT TESTING | Dec 19, 1991 | Abandoned |
Array
(
[id] => 3117893
[patent_doc_number] => 05418791
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-23
[patent_title] => 'Semiconductor integrated circuit having test circuit'
[patent_app_type] => 1
[patent_app_number] => 7/810750
[patent_app_country] => US
[patent_app_date] => 1991-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 5943
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/418/05418791.pdf
[firstpage_image] =>[orig_patent_app_number] => 810750
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/810750 | Semiconductor integrated circuit having test circuit | Dec 18, 1991 | Issued |
07/810072 | METHOD AND APPARATUS FOR PREDICTING TRANSMISSION SYSTEM ERRORS AND FAILURES | Dec 18, 1991 | Abandoned |
07/809354 | ASYNCHRONOUS REPLICA MANAGEMENT IN SHARED NOTHING ARCHITECTURES | Dec 17, 1991 | Abandoned |
Array
(
[id] => 3119238
[patent_doc_number] => 05408477
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-18
[patent_title] => 'Error correction method'
[patent_app_type] => 1
[patent_app_number] => 7/806161
[patent_app_country] => US
[patent_app_date] => 1991-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 7249
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 347
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/408/05408477.pdf
[firstpage_image] =>[orig_patent_app_number] => 806161
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/806161 | Error correction method | Dec 11, 1991 | Issued |
Array
(
[id] => 3436021
[patent_doc_number] => 05404362
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-04
[patent_title] => 'Very low jitter clock recovery from serial audio data'
[patent_app_type] => 1
[patent_app_number] => 7/802332
[patent_app_country] => US
[patent_app_date] => 1991-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
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[patent_no_of_claims] => 7
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/404/05404362.pdf
[firstpage_image] =>[orig_patent_app_number] => 802332
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/802332 | Very low jitter clock recovery from serial audio data | Dec 3, 1991 | Issued |
Array
(
[id] => 3001908
[patent_doc_number] => 05347519
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-09-13
[patent_title] => 'Preprogramming testing in a field programmable gate array'
[patent_app_type] => 1
[patent_app_number] => 7/801237
[patent_app_country] => US
[patent_app_date] => 1991-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 30
[patent_no_of_words] => 18053
[patent_no_of_claims] => 14
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/347/05347519.pdf
[firstpage_image] =>[orig_patent_app_number] => 801237
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/801237 | Preprogramming testing in a field programmable gate array | Dec 2, 1991 | Issued |
Array
(
[id] => 3067090
[patent_doc_number] => 05357509
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-10-18
[patent_title] => 'Data writing during process of data restoration in array disk storage system'
[patent_app_type] => 1
[patent_app_number] => 7/801572
[patent_app_country] => US
[patent_app_date] => 1991-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
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[pdf_file] => patents/05/357/05357509.pdf
[firstpage_image] =>[orig_patent_app_number] => 801572
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/801572 | Data writing during process of data restoration in array disk storage system | Dec 1, 1991 | Issued |
07/788677 | ERROR PULSE WIDTH EXPANDING CIRCUIT | Nov 5, 1991 | Abandoned |
Array
(
[id] => 3020988
[patent_doc_number] => 05333140
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-07-26
[patent_title] => 'Servowriter/certifier'
[patent_app_type] => 1
[patent_app_number] => 7/770642
[patent_app_country] => US
[patent_app_date] => 1991-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/333/05333140.pdf
[firstpage_image] =>[orig_patent_app_number] => 770642
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/770642 | Servowriter/certifier | Oct 2, 1991 | Issued |