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Benjamin Morales Fernandez

Examiner (ID: 3629, Phone: (571)270-5797 , Office: P/2624 )

Most Active Art Unit
2624
Art Unit(s)
2698, 2624, 2617
Total Applications
242
Issued Applications
182
Pending Applications
0
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3795388 [patent_doc_number] => 05758052 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Network management method using redundant distributed control processors' [patent_app_type] => 1 [patent_app_number] => 7/771063 [patent_app_country] => US [patent_app_date] => 1991-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3129 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/758/05758052.pdf [firstpage_image] =>[orig_patent_app_number] => 771063 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/771063
Network management method using redundant distributed control processors Oct 1, 1991 Issued
Array ( [id] => 3083197 [patent_doc_number] => 05337317 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-09 [patent_title] => 'Minimizing the programming time in a semiconductor integrated memory circuit having an error correction function' [patent_app_type] => 1 [patent_app_number] => 7/771001 [patent_app_country] => US [patent_app_date] => 1991-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4526 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 338 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/337/05337317.pdf [firstpage_image] =>[orig_patent_app_number] => 771001 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/771001
Minimizing the programming time in a semiconductor integrated memory circuit having an error correction function Sep 30, 1991 Issued
Array ( [id] => 3472736 [patent_doc_number] => 05469452 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-21 [patent_title] => 'Viterbi decoder bit efficient chainback memory method and decoder incorporating same' [patent_app_type] => 1 [patent_app_number] => 7/767167 [patent_app_country] => US [patent_app_date] => 1991-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 13404 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/469/05469452.pdf [firstpage_image] =>[orig_patent_app_number] => 767167 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/767167
Viterbi decoder bit efficient chainback memory method and decoder incorporating same Sep 26, 1991 Issued
Array ( [id] => 2949073 [patent_doc_number] => 05260950 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-09 [patent_title] => 'Boundary-scan input circuit for a reset pin' [patent_app_type] => 1 [patent_app_number] => 7/761141 [patent_app_country] => US [patent_app_date] => 1991-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3240 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/260/05260950.pdf [firstpage_image] =>[orig_patent_app_number] => 761141 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/761141
Boundary-scan input circuit for a reset pin Sep 16, 1991 Issued
07/757162 BOUNDARY-SCAN INTERCONNECT TEST METHOD Sep 9, 1991 Abandoned
Array ( [id] => 3097206 [patent_doc_number] => 05285459 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-08 [patent_title] => 'HDB3 code violation detector' [patent_app_type] => 1 [patent_app_number] => 7/755761 [patent_app_country] => US [patent_app_date] => 1991-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7510 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/285/05285459.pdf [firstpage_image] =>[orig_patent_app_number] => 755761 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/755761
HDB3 code violation detector Sep 5, 1991 Issued
07/732040 MIRRORED MEMORY MULTI-PROCESSOR SYSTEM Jul 17, 1991 Abandoned
Array ( [id] => 3095136 [patent_doc_number] => 05280607 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-18 [patent_title] => 'Method and apparatus for tolerating faults in mesh architectures' [patent_app_type] => 1 [patent_app_number] => 7/723287 [patent_app_country] => US [patent_app_date] => 1991-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 6 [patent_no_of_words] => 8828 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/280/05280607.pdf [firstpage_image] =>[orig_patent_app_number] => 723287 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/723287
Method and apparatus for tolerating faults in mesh architectures Jun 27, 1991 Issued
07/710405 DIGITAL DATA PROCESSING SYSTEM WITH ERROR DETECTION AND ERROR CORRECTION CODING Jun 4, 1991 Abandoned
Array ( [id] => 3672261 [patent_doc_number] => 05649090 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Fault tolerant multiprocessor computer system' [patent_app_type] => 1 [patent_app_number] => 7/708965 [patent_app_country] => US [patent_app_date] => 1991-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5657 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 476 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649090.pdf [firstpage_image] =>[orig_patent_app_number] => 708965 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/708965
Fault tolerant multiprocessor computer system May 30, 1991 Issued
Array ( [id] => 3026481 [patent_doc_number] => 05341386 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-23 [patent_title] => 'Viterbi equalizer and recording/reproducing device using the same' [patent_app_type] => 1 [patent_app_number] => 7/705065 [patent_app_country] => US [patent_app_date] => 1991-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 3858 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/341/05341386.pdf [firstpage_image] =>[orig_patent_app_number] => 705065 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/705065
Viterbi equalizer and recording/reproducing device using the same May 22, 1991 Issued
Array ( [id] => 3471597 [patent_doc_number] => 05392291 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Fault-tolerant CITO communication system' [patent_app_type] => 1 [patent_app_number] => 7/703025 [patent_app_country] => US [patent_app_date] => 1991-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3052 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/392/05392291.pdf [firstpage_image] =>[orig_patent_app_number] => 703025 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/703025
Fault-tolerant CITO communication system May 19, 1991 Issued
07/699065 FILTERED SIGNAL VALIDATION May 12, 1991 Abandoned
Array ( [id] => 3033499 [patent_doc_number] => 05289476 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-22 [patent_title] => 'Transmission mode detection in a modulated communication system' [patent_app_type] => 1 [patent_app_number] => 7/698445 [patent_app_country] => US [patent_app_date] => 1991-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5860 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/289/05289476.pdf [firstpage_image] =>[orig_patent_app_number] => 698445 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/698445
Transmission mode detection in a modulated communication system May 9, 1991 Issued
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