Search

Benjamin P. Geib

Examiner (ID: 2092)

Most Active Art Unit
2183
Art Unit(s)
2123, 2183, 2181
Total Applications
705
Issued Applications
612
Pending Applications
10
Abandoned Applications
93

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13541667 [patent_doc_number] => 20180322380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => VIRTUAL ASSISTANT CONFIGURED TO RECOMMENDED ACTIONS IN FURTHERANCE OF AN EXISTING CONVERSATION [patent_app_type] => utility [patent_app_number] => 15/588055 [patent_app_country] => US [patent_app_date] => 2017-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14098 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15588055 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/588055
Virtual assistant configured to recommended actions in furtherance of an existing conversation May 4, 2017 Issued
Array ( [id] => 13526813 [patent_doc_number] => 20180314949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => COGNITIVE BASED DECISION SUPPORT SYSTEM FOR AGRICULTURE [patent_app_type] => utility [patent_app_number] => 15/497560 [patent_app_country] => US [patent_app_date] => 2017-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10917 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15497560 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/497560
Cognitive based decision support system for agriculture Apr 25, 2017 Issued
Array ( [id] => 13512907 [patent_doc_number] => 20180307996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => METHOD, ONE OR MORE COMPUTER READABLE STORAGE MEDIUMS, COMPUTER PROGRAM PRODUCT, AND COMPUTER [patent_app_type] => utility [patent_app_number] => 15/492368 [patent_app_country] => US [patent_app_date] => 2017-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10895 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15492368 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/492368
Probabilistic estimation of node values Apr 19, 2017 Issued
Array ( [id] => 11838628 [patent_doc_number] => 20170220348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'Performing Rounding Operations Responsive To An Instruction' [patent_app_type] => utility [patent_app_number] => 15/485372 [patent_app_country] => US [patent_app_date] => 2017-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5241 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15485372 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/485372
Performing rounding operations responsive to an instruction Apr 11, 2017 Issued
Array ( [id] => 11838629 [patent_doc_number] => 20170220349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'Performing Rounding Operations Responsive To An Instruction' [patent_app_type] => utility [patent_app_number] => 15/485378 [patent_app_country] => US [patent_app_date] => 2017-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5244 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15485378 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/485378
Performing rounding operations responsive to an instruction Apr 11, 2017 Issued
Array ( [id] => 11838627 [patent_doc_number] => 20170220347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'Performing Rounding Operations Responsive To An Instruction' [patent_app_type] => utility [patent_app_number] => 15/485356 [patent_app_country] => US [patent_app_date] => 2017-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5242 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15485356 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/485356
Performing rounding operations responsive to an instruction Apr 11, 2017 Issued
Array ( [id] => 17455336 [patent_doc_number] => 11270199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-08 [patent_title] => Analogue electronic neural network [patent_app_type] => utility [patent_app_number] => 16/078769 [patent_app_country] => US [patent_app_date] => 2017-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4546 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16078769 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/078769
Analogue electronic neural network Feb 16, 2017 Issued
Array ( [id] => 11917255 [patent_doc_number] => 09785440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-10 [patent_title] => 'Techniques for metadata processing' [patent_app_type] => utility [patent_app_number] => 15/426098 [patent_app_country] => US [patent_app_date] => 2017-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 90 [patent_figures_cnt] => 100 [patent_no_of_words] => 77350 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15426098 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/426098
Techniques for metadata processing Feb 6, 2017 Issued
Array ( [id] => 18104691 [patent_doc_number] => 11544582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Predictive modelling to score customer leads using data analytics using an end-to-end automated, sampled approach with iterative local and global optimization [patent_app_type] => utility [patent_app_number] => 15/423541 [patent_app_country] => US [patent_app_date] => 2017-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3530 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15423541 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/423541
Predictive modelling to score customer leads using data analytics using an end-to-end automated, sampled approach with iterative local and global optimization Feb 1, 2017 Issued
Array ( [id] => 13318643 [patent_doc_number] => 20180210859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => COMBINING OF SEVERAL EXECUTION UNITS TO COMPUTE A SINGLE WIDE SCALAR RESULT [patent_app_type] => utility [patent_app_number] => 15/412429 [patent_app_country] => US [patent_app_date] => 2017-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4712 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15412429 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/412429
Combining of several execution units to compute a single wide scalar result Jan 22, 2017 Issued
Array ( [id] => 13304321 [patent_doc_number] => 20180203697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => GUARDED STORAGE EVENT HANDLING DURING TRANSACTIONAL EXECUTION [patent_app_type] => utility [patent_app_number] => 15/409643 [patent_app_country] => US [patent_app_date] => 2017-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15224 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15409643 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/409643
Guarded storage event handling during transactional execution Jan 18, 2017 Issued
Array ( [id] => 16171481 [patent_doc_number] => 10713048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Conditional branch to an indirectly specified location [patent_app_type] => utility [patent_app_number] => 15/409614 [patent_app_country] => US [patent_app_date] => 2017-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7066 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15409614 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/409614
Conditional branch to an indirectly specified location Jan 18, 2017 Issued
Array ( [id] => 15700975 [patent_doc_number] => 10606663 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Processor mode switching [patent_app_type] => utility [patent_app_number] => 15/407762 [patent_app_country] => US [patent_app_date] => 2017-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4089 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15407762 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/407762
Processor mode switching Jan 16, 2017 Issued
Array ( [id] => 13304315 [patent_doc_number] => 20180203694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => Execution Unit with Selective Instruction Pipeline Bypass [patent_app_type] => utility [patent_app_number] => 15/406996 [patent_app_country] => US [patent_app_date] => 2017-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12070 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15406996 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/406996
Execution Unit with Selective Instruction Pipeline Bypass Jan 15, 2017 Abandoned
Array ( [id] => 11606498 [patent_doc_number] => 20170123801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'LATENT MODIFICATION INSTRUCTION FOR TRANSACTIONAL EXECUTION' [patent_app_type] => utility [patent_app_number] => 15/403275 [patent_app_country] => US [patent_app_date] => 2017-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 21879 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15403275 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/403275
Latent modification instruction for transactional execution Jan 10, 2017 Issued
Array ( [id] => 11606499 [patent_doc_number] => 20170123802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'LATENT MODIFICATION INSTRUCTION FOR TRANSACTIONAL EXECUTION' [patent_app_type] => utility [patent_app_number] => 15/403283 [patent_app_country] => US [patent_app_date] => 2017-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 21881 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15403283 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/403283
Latent modification instruction for transactional execution Jan 10, 2017 Issued
Array ( [id] => 11651451 [patent_doc_number] => 20170147352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'METHOD OF SYNCHRONIZING INDEPENDENT FUNCTIONAL UNIT' [patent_app_type] => utility [patent_app_number] => 15/401204 [patent_app_country] => US [patent_app_date] => 2017-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3398 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15401204 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/401204
Method of synchronizing independent functional unit Jan 8, 2017 Issued
Array ( [id] => 11530965 [patent_doc_number] => 20170090943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'EXTERNAL INTRINSIC INTERFACE' [patent_app_type] => utility [patent_app_number] => 15/375874 [patent_app_country] => US [patent_app_date] => 2016-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2742 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15375874 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/375874
External intrinsic interface Dec 11, 2016 Issued
Array ( [id] => 17543263 [patent_doc_number] => 11308388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-19 [patent_title] => Electronic circuit, particularly for the implementation of neural networks with multiple levels of precision [patent_app_type] => utility [patent_app_number] => 15/781680 [patent_app_country] => US [patent_app_date] => 2016-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5129 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15781680 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/781680
Electronic circuit, particularly for the implementation of neural networks with multiple levels of precision Dec 6, 2016 Issued
Array ( [id] => 13003845 [patent_doc_number] => 10025591 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Instruction for element offset calculation in a multi-dimensional array [patent_app_type] => utility [patent_app_number] => 15/363785 [patent_app_country] => US [patent_app_date] => 2016-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 28 [patent_no_of_words] => 14974 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15363785 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/363785
Instruction for element offset calculation in a multi-dimensional array Nov 28, 2016 Issued
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