Search

Benjamin P. Geib

Examiner (ID: 2092)

Most Active Art Unit
2183
Art Unit(s)
2123, 2183, 2181
Total Applications
705
Issued Applications
612
Pending Applications
10
Abandoned Applications
93

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11651446 [patent_doc_number] => 20170147347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'METHOD OF SYNCHRONIZING INDEPENDENT FUNCTIONAL UNIT' [patent_app_type] => utility [patent_app_number] => 14/950452 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3397 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950452 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/950452
Method of synchronizing independent functional unit Nov 23, 2015 Issued
Array ( [id] => 11973504 [patent_doc_number] => 20170277658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-28 [patent_title] => 'METHOD AND APPARATUS FOR DISTRIBUTED AND COOPERATIVE COMPUTATION IN ARTIFICIAL NEURAL NETWORKS' [patent_app_type] => utility [patent_app_number] => 15/521856 [patent_app_country] => US [patent_app_date] => 2015-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 16440 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15521856 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/521856
Method and apparatus for distributed and cooperative computation in artificial neural networks Nov 18, 2015 Issued
Array ( [id] => 14009263 [patent_doc_number] => 10223090 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Branch look-ahead system apparatus and method for branch look-ahead microprocessors [patent_app_type] => utility [patent_app_number] => 14/922112 [patent_app_country] => US [patent_app_date] => 2015-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 9632 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14922112 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/922112
Branch look-ahead system apparatus and method for branch look-ahead microprocessors Oct 22, 2015 Issued
Array ( [id] => 10687878 [patent_doc_number] => 20160034022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'DYNAMIC CORE SWITCHING' [patent_app_type] => utility [patent_app_number] => 14/880670 [patent_app_country] => US [patent_app_date] => 2015-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 23592 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14880670 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/880670
DYNAMIC CORE SWITCHING Oct 11, 2015 Abandoned
Array ( [id] => 10746062 [patent_doc_number] => 20160092213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'COMPUTER SYSTEM INCLUDING RECONFIGURABLE ARITHMETIC DEVICE WITH NETWORK OF PROCESSOR ELEMENTS' [patent_app_type] => utility [patent_app_number] => 14/868296 [patent_app_country] => US [patent_app_date] => 2015-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9213 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14868296 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/868296
Computer system including reconfigurable arithmetic device with network of processor elements Sep 27, 2015 Issued
Array ( [id] => 11738978 [patent_doc_number] => 09703560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-11 [patent_title] => 'Collecting transactional execution characteristics during transactional execution' [patent_app_type] => utility [patent_app_number] => 14/830872 [patent_app_country] => US [patent_app_date] => 2015-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 22502 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14830872 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/830872
Collecting transactional execution characteristics during transactional execution Aug 19, 2015 Issued
Array ( [id] => 11509128 [patent_doc_number] => 09600287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-21 [patent_title] => 'Latent modification instruction for transactional execution' [patent_app_type] => utility [patent_app_number] => 14/830073 [patent_app_country] => US [patent_app_date] => 2015-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 21878 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14830073 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/830073
Latent modification instruction for transactional execution Aug 18, 2015 Issued
Array ( [id] => 12372714 [patent_doc_number] => 09959123 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-01 [patent_title] => Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor [patent_app_type] => utility [patent_app_number] => 14/827284 [patent_app_country] => US [patent_app_date] => 2015-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5773 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14827284 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/827284
Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor Aug 14, 2015 Issued
Array ( [id] => 13817585 [patent_doc_number] => 10185561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-22 [patent_title] => Processor with efficient memory access [patent_app_type] => utility [patent_app_number] => 14/794835 [patent_app_country] => US [patent_app_date] => 2015-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 13107 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14794835 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/794835
Processor with efficient memory access Jul 8, 2015 Issued
Array ( [id] => 15731883 [patent_doc_number] => 10614374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-07 [patent_title] => Classifying online system users based on their propensity to adopt innovations in a subject area [patent_app_type] => utility [patent_app_number] => 14/742495 [patent_app_country] => US [patent_app_date] => 2015-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 12513 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14742495 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/742495
Classifying online system users based on their propensity to adopt innovations in a subject area Jun 16, 2015 Issued
Array ( [id] => 12100983 [patent_doc_number] => 09858078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-02 [patent_title] => 'Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor' [patent_app_type] => utility [patent_app_number] => 14/728534 [patent_app_country] => US [patent_app_date] => 2015-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5876 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14728534 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/728534
Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor Jun 1, 2015 Issued
Array ( [id] => 12513591 [patent_doc_number] => 10001995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-19 [patent_title] => Packed data alignment plus compute instructions, processors, methods, and systems [patent_app_type] => utility [patent_app_number] => 14/728693 [patent_app_country] => US [patent_app_date] => 2015-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 21190 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14728693 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/728693
Packed data alignment plus compute instructions, processors, methods, and systems Jun 1, 2015 Issued
Array ( [id] => 12373083 [patent_doc_number] => 09959246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-01 [patent_title] => Vector processor configured to operate on variable length vectors using implicitly typed instructions [patent_app_type] => utility [patent_app_number] => 14/728522 [patent_app_country] => US [patent_app_date] => 2015-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 21556 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14728522 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/728522
Vector processor configured to operate on variable length vectors using implicitly typed instructions Jun 1, 2015 Issued
Array ( [id] => 16217326 [patent_doc_number] => 10733140 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Vector processor configured to operate on variable length vectors using instructions that change element widths [patent_app_type] => utility [patent_app_number] => 14/727051 [patent_app_country] => US [patent_app_date] => 2015-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 23561 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14727051 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/727051
Vector processor configured to operate on variable length vectors using instructions that change element widths May 31, 2015 Issued
Array ( [id] => 11027392 [patent_doc_number] => 20160224346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS USING INSTRUCTIONS TO COMBINE AND SPLIT VECTORS' [patent_app_type] => utility [patent_app_number] => 14/727076 [patent_app_country] => US [patent_app_date] => 2015-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 23529 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14727076 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/727076
Vector processor configured to operate on variable length vectors using instructions to combine and split vectors May 31, 2015 Issued
Array ( [id] => 11027385 [patent_doc_number] => 20160224340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS USING ONE OR MORE COMPLEX ARITHMETIC INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 14/724061 [patent_app_country] => US [patent_app_date] => 2015-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 23790 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14724061 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/724061
Vector processor configured to operate on variable length vectors using one or more complex arithmetic instructions May 27, 2015 Issued
Array ( [id] => 10462130 [patent_doc_number] => 20150347144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'Decoding Instructions That Are Modified By One Or More Other Instructions' [patent_app_type] => utility [patent_app_number] => 14/722292 [patent_app_country] => US [patent_app_date] => 2015-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10601 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14722292 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/722292
Decoding instructions that are modified by one or more other instructions May 26, 2015 Issued
Array ( [id] => 11314015 [patent_doc_number] => 20160350124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'ENABLING END OF TRANSACTION DETECTION USING SPECULATIVE LOOK AHEAD' [patent_app_type] => utility [patent_app_number] => 14/722179 [patent_app_country] => US [patent_app_date] => 2015-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 21933 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14722179 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/722179
Enabling end of transaction detection using speculative look ahead May 26, 2015 Issued
Array ( [id] => 10764049 [patent_doc_number] => 20160110203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'COMPUTER SYSTEM FOR NOTIFYING SIGNAL CHANGE EVENT THROUGH CACHE STASHING' [patent_app_type] => utility [patent_app_number] => 14/720986 [patent_app_country] => US [patent_app_date] => 2015-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7521 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14720986 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/720986
Computer system for notifying signal change event through cache stashing May 25, 2015 Issued
Array ( [id] => 13767295 [patent_doc_number] => 10175989 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => VLIW type instruction packet structure and processor suitable for processing such an instruction packet [patent_app_type] => utility [patent_app_number] => 15/312961 [patent_app_country] => US [patent_app_date] => 2015-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4603 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15312961 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/312961
VLIW type instruction packet structure and processor suitable for processing such an instruction packet Apr 26, 2015 Issued
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