Search

Benjamin P. Geib

Examiner (ID: 5552, Phone: (571)272-8628 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2181, 2123
Total Applications
703
Issued Applications
612
Pending Applications
6
Abandoned Applications
93

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12018631 [patent_doc_number] => 09811336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-07 [patent_title] => 'Determining processor offsets to synchronize processor time values' [patent_app_type] => utility [patent_app_number] => 14/504323 [patent_app_country] => US [patent_app_date] => 2014-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5089 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14504323 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/504323
Determining processor offsets to synchronize processor time values Sep 30, 2014 Issued
Array ( [id] => 9903407 [patent_doc_number] => 20150058607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'CONFIDENCE THRESHOLD-BASED OPPOSING BRANCH PATH EXECUTION FOR BRANCH PREDICTION' [patent_app_type] => utility [patent_app_number] => 14/501452 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6147 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14501452 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/501452
Confidence threshold-based opposing branch path execution for branch prediction Sep 29, 2014 Issued
Array ( [id] => 12255989 [patent_doc_number] => 09928132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-27 [patent_title] => 'Dynamic accessing of execution elements through modification of issue rules' [patent_app_type] => utility [patent_app_number] => 14/501326 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5567 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14501326 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/501326
Dynamic accessing of execution elements through modification of issue rules Sep 29, 2014 Issued
Array ( [id] => 11996175 [patent_doc_number] => 20170300330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-19 [patent_title] => 'ISA EXTENSIONS FOR SYNCHRONOUS COALESCED ACCESSES' [patent_app_type] => utility [patent_app_number] => 14/476848 [patent_app_country] => US [patent_app_date] => 2014-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7195 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14476848 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/476848
ISA extensions for synchronous coalesced accesses Sep 3, 2014 Issued
Array ( [id] => 9814500 [patent_doc_number] => 20150026445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'PROCESSOR TESTING' [patent_app_type] => utility [patent_app_number] => 14/475606 [patent_app_country] => US [patent_app_date] => 2014-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7300 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14475606 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/475606
Processor testing Sep 2, 2014 Issued
Array ( [id] => 11488493 [patent_doc_number] => 09594564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-14 [patent_title] => 'Arithmetic processing device and control method of arithmetic processing device' [patent_app_type] => utility [patent_app_number] => 14/318732 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 13410 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14318732 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/318732
Arithmetic processing device and control method of arithmetic processing device Jun 29, 2014 Issued
Array ( [id] => 10493707 [patent_doc_number] => 20150378729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'COLLECTING TRANSACTIONAL EXECUTION CHARACTERISTICS DURING TRANSACTIONAL EXECUTION' [patent_app_type] => utility [patent_app_number] => 14/318782 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 22481 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14318782 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/318782
Collecting transactional execution characteristics during transactional execution Jun 29, 2014 Issued
Array ( [id] => 10493709 [patent_doc_number] => 20150378731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'APPARATUS AND METHOD FOR EFFICIENTLY IMPLEMENTING A PROCESSOR PIPELINE' [patent_app_type] => utility [patent_app_number] => 14/319265 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 25119 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14319265 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/319265
Apparatus and method for efficiently implementing a processor pipeline Jun 29, 2014 Issued
Array ( [id] => 11509126 [patent_doc_number] => 09600286 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-21 [patent_title] => 'Latent modification instruction for transactional execution' [patent_app_type] => utility [patent_app_number] => 14/318752 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 21879 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14318752 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/318752
Latent modification instruction for transactional execution Jun 29, 2014 Issued
Array ( [id] => 11482223 [patent_doc_number] => 09588769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Processor that leapfrogs MOV instructions' [patent_app_type] => utility [patent_app_number] => 14/315122 [patent_app_country] => US [patent_app_date] => 2014-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6539 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14315122 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/315122
Processor that leapfrogs MOV instructions Jun 24, 2014 Issued
Array ( [id] => 9800785 [patent_doc_number] => 20150012728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-08 [patent_title] => 'SYSTEM FOR PROVIDING TRACE DATA IN A DATA PROCESSOR HAVING A PIPELINED ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/271886 [patent_app_country] => US [patent_app_date] => 2014-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8422 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14271886 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/271886
System for providing trace data in a data processor having a pipelined architecture May 6, 2014 Issued
Array ( [id] => 11700672 [patent_doc_number] => 09690587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-27 [patent_title] => 'Variable updates of branch prediction states' [patent_app_type] => utility [patent_app_number] => 14/247813 [patent_app_country] => US [patent_app_date] => 2014-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5967 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14247813 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/247813
Variable updates of branch prediction states Apr 7, 2014 Issued
Array ( [id] => 9645033 [patent_doc_number] => 20140223146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'Blank Bit and Processor Instructions Employing the Blank Bit' [patent_app_type] => utility [patent_app_number] => 14/248283 [patent_app_country] => US [patent_app_date] => 2014-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6725 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14248283 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/248283
Blank bit and processor instructions employing the blank bit Apr 7, 2014 Issued
Array ( [id] => 11206839 [patent_doc_number] => 09436465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Moving average processing in processor and processor' [patent_app_type] => utility [patent_app_number] => 14/246757 [patent_app_country] => US [patent_app_date] => 2014-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 26 [patent_no_of_words] => 7098 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14246757 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/246757
Moving average processing in processor and processor Apr 6, 2014 Issued
Array ( [id] => 11550382 [patent_doc_number] => 09619231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-11 [patent_title] => 'Programmable CPU register hardware context swap mechanism' [patent_app_type] => utility [patent_app_number] => 14/200417 [patent_app_country] => US [patent_app_date] => 2014-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6002 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14200417 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/200417
Programmable CPU register hardware context swap mechanism Mar 6, 2014 Issued
Array ( [id] => 10976990 [patent_doc_number] => 20140380026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-25 [patent_title] => 'CONTROL DEVICE AND ACCESS SYSTEM UTILIZING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/195089 [patent_app_country] => US [patent_app_date] => 2014-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2115 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14195089 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/195089
Control device and access system utilizing the same Mar 2, 2014 Issued
Array ( [id] => 11193216 [patent_doc_number] => 09424032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-23 [patent_title] => 'List vector processing apparatus, list vector processing method, storage medium, compiler, and information processing apparatus' [patent_app_type] => utility [patent_app_number] => 14/188563 [patent_app_country] => US [patent_app_date] => 2014-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 9830 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14188563 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/188563
List vector processing apparatus, list vector processing method, storage medium, compiler, and information processing apparatus Feb 23, 2014 Issued
Array ( [id] => 11193240 [patent_doc_number] => 09424055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-23 [patent_title] => 'Multi-function instruction that determines whether functions are installed on a system' [patent_app_type] => utility [patent_app_number] => 14/144830 [patent_app_country] => US [patent_app_date] => 2013-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 30 [patent_no_of_words] => 6028 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14144830 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/144830
Multi-function instruction that determines whether functions are installed on a system Dec 30, 2013 Issued
Array ( [id] => 13199457 [patent_doc_number] => 10114647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Reducing data hazards in pipelined processors to provide high processor utilization [patent_app_type] => utility [patent_app_number] => 14/101902 [patent_app_country] => US [patent_app_date] => 2013-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 6675 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14101902 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/101902
Reducing data hazards in pipelined processors to provide high processor utilization Dec 9, 2013 Issued
Array ( [id] => 9398429 [patent_doc_number] => 20140095835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'PERFORMING PREDECODE-TIME OPTIMIZED INSTRUCTIONS IN CONJUNCTION WITH PREDECODE TIME OPTIMIZED INSTRUCTION SEQUENCE CACHING' [patent_app_type] => utility [patent_app_number] => 14/100044 [patent_app_country] => US [patent_app_date] => 2013-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6295 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14100044 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/100044
Performing predecode-time optimized instructions in conjunction with predecode time optimized instruction sequence caching Dec 8, 2013 Issued
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