
Benjamin P. Geib
Examiner (ID: 5552, Phone: (571)272-8628 , Office: P/2183 )
| Most Active Art Unit | 2183 |
| Art Unit(s) | 2183, 2181, 2123 |
| Total Applications | 703 |
| Issued Applications | 612 |
| Pending Applications | 6 |
| Abandoned Applications | 93 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11775074
[patent_doc_number] => 09384000
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-07-05
[patent_title] => 'Caching optimized internal instructions in loop buffer'
[patent_app_type] => utility
[patent_app_number] => 14/090318
[patent_app_country] => US
[patent_app_date] => 2013-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7672
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14090318
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/090318 | Caching optimized internal instructions in loop buffer | Nov 25, 2013 | Issued |
Array
(
[id] => 11924538
[patent_doc_number] => 09792121
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-10-17
[patent_title] => 'Microprocessor that fuses if-then instructions'
[patent_app_type] => utility
[patent_app_number] => 14/066520
[patent_app_country] => US
[patent_app_date] => 2013-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 10544
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14066520
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/066520 | Microprocessor that fuses if-then instructions | Oct 28, 2013 | Issued |
Array
(
[id] => 11206846
[patent_doc_number] => 09436472
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-09-06
[patent_title] => 'Register renaming system using multi-bank physical register mapping table and method thereof'
[patent_app_type] => utility
[patent_app_number] => 14/064936
[patent_app_country] => US
[patent_app_date] => 2013-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 16390
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14064936
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/064936 | Register renaming system using multi-bank physical register mapping table and method thereof | Oct 27, 2013 | Issued |
Array
(
[id] => 9320622
[patent_doc_number] => 20140052960
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-20
[patent_title] => 'APPARATUS AND METHOD FOR GENERATING VLIW, AND PROCESSOR AND METHOD FOR PROCESSING VLIW'
[patent_app_type] => utility
[patent_app_number] => 14/064497
[patent_app_country] => US
[patent_app_date] => 2013-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4432
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14064497
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/064497 | Apparatus and method for generating VLIW, and processor and method for processing VLIW | Oct 27, 2013 | Issued |
Array
(
[id] => 10644272
[patent_doc_number] => 09361141
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-06-07
[patent_title] => 'Systems and methods for controlling, by a hypervisor, access to physical resources'
[patent_app_type] => utility
[patent_app_number] => 14/035386
[patent_app_country] => US
[patent_app_date] => 2013-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 8651
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14035386
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/035386 | Systems and methods for controlling, by a hypervisor, access to physical resources | Sep 23, 2013 | Issued |
Array
(
[id] => 11258334
[patent_doc_number] => 09483233
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-11-01
[patent_title] => 'Methods and apparatus for matrix decompositions in programmable logic devices'
[patent_app_type] => utility
[patent_app_number] => 14/025621
[patent_app_country] => US
[patent_app_date] => 2013-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 20
[patent_no_of_words] => 8411
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14025621
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/025621 | Methods and apparatus for matrix decompositions in programmable logic devices | Sep 11, 2013 | Issued |
Array
(
[id] => 9264802
[patent_doc_number] => 20130346731
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-12-26
[patent_title] => 'INSTRUCTION TRACKING SYSTEM FOR PROCESSORS'
[patent_app_type] => utility
[patent_app_number] => 13/975373
[patent_app_country] => US
[patent_app_date] => 2013-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 10447
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13975373
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/975373 | Instruction tracking system for processors | Aug 25, 2013 | Issued |
Array
(
[id] => 10130927
[patent_doc_number] => 09164762
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-10-20
[patent_title] => 'Rotate instructions that complete execution without reading carry flag'
[patent_app_type] => utility
[patent_app_number] => 13/947958
[patent_app_country] => US
[patent_app_date] => 2013-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 7435
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13947958
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/947958 | Rotate instructions that complete execution without reading carry flag | Jul 21, 2013 | Issued |
Array
(
[id] => 9540094
[patent_doc_number] => 20140164742
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-06-12
[patent_title] => 'APPARATUS AND METHOD FOR MAPPING ARCHITECTURAL REGISTERS TO PHYSICAL REGISTERS'
[patent_app_type] => utility
[patent_app_number] => 13/927552
[patent_app_country] => US
[patent_app_date] => 2013-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6814
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13927552
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/927552 | Apparatus and method for mapping architectural registers to physical registers | Jun 25, 2013 | Issued |
Array
(
[id] => 9096666
[patent_doc_number] => 20130275977
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-17
[patent_title] => 'VIRTUAL MACHINE PACKING METHOD USING SCARCITY'
[patent_app_type] => utility
[patent_app_number] => 13/914240
[patent_app_country] => US
[patent_app_date] => 2013-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5449
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13914240
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/914240 | Virtual machine packing method using scarcity | Jun 9, 2013 | Issued |
Array
(
[id] => 8991872
[patent_doc_number] => 20130219153
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-08-22
[patent_title] => 'Load/Move and Duplicate Instructions for a Processor'
[patent_app_type] => utility
[patent_app_number] => 13/843815
[patent_app_country] => US
[patent_app_date] => 2013-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4672
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13843815
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/843815 | Load/move and duplicate instructions for a processor | Mar 14, 2013 | Issued |
Array
(
[id] => 9109885
[patent_doc_number] => 20130283017
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-24
[patent_title] => 'HARD OBJECT: CONSTRAINING CONTROL FLOW AND PROVIDING LIGHTWEIGHT KERNEL CROSSINGS'
[patent_app_type] => utility
[patent_app_number] => 13/804633
[patent_app_country] => US
[patent_app_date] => 2013-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 32
[patent_no_of_words] => 36656
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13804633
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/804633 | Hard object: constraining control flow and providing lightweight kernel crossings | Mar 13, 2013 | Issued |
Array
(
[id] => 10562515
[patent_doc_number] => 09286192
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-03-15
[patent_title] => 'Modifying run-time-instrumentation controls from a lesser-privileged state'
[patent_app_type] => utility
[patent_app_number] => 13/792283
[patent_app_country] => US
[patent_app_date] => 2013-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 17242
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 294
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13792283
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/792283 | Modifying run-time-instrumentation controls from a lesser-privileged state | Mar 10, 2013 | Issued |
Array
(
[id] => 10562515
[patent_doc_number] => 09286192
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-03-15
[patent_title] => 'Modifying run-time-instrumentation controls from a lesser-privileged state'
[patent_app_type] => utility
[patent_app_number] => 13/792283
[patent_app_country] => US
[patent_app_date] => 2013-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 17242
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 294
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13792283
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/792283 | Modifying run-time-instrumentation controls from a lesser-privileged state | Mar 10, 2013 | Issued |
Array
(
[id] => 10562515
[patent_doc_number] => 09286192
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-03-15
[patent_title] => 'Modifying run-time-instrumentation controls from a lesser-privileged state'
[patent_app_type] => utility
[patent_app_number] => 13/792283
[patent_app_country] => US
[patent_app_date] => 2013-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 17242
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 294
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13792283
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/792283 | Modifying run-time-instrumentation controls from a lesser-privileged state | Mar 10, 2013 | Issued |
Array
(
[id] => 10562589
[patent_doc_number] => 09286267
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-03-15
[patent_title] => 'Performing rounding operations responsive to an instruction'
[patent_app_type] => utility
[patent_app_number] => 13/793648
[patent_app_country] => US
[patent_app_date] => 2013-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5182
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13793648
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/793648 | Performing rounding operations responsive to an instruction | Mar 10, 2013 | Issued |
Array
(
[id] => 9513233
[patent_doc_number] => 20140149726
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-05-29
[patent_title] => 'ESTABLISHING A BRANCH TARGET INSTRUCTION CACHE (BTIC) ENTRY FOR SUBROUTINE RETURNS TO REDUCE EXECUTION PIPELINE BUBBLES, AND RELATED SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA'
[patent_app_type] => utility
[patent_app_number] => 13/792335
[patent_app_country] => US
[patent_app_date] => 2013-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 9223
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13792335
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/792335 | Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce execution pipeline bubbles, and related systems, methods, and computer-readable media | Mar 10, 2013 | Issued |
Array
(
[id] => 10562515
[patent_doc_number] => 09286192
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-03-15
[patent_title] => 'Modifying run-time-instrumentation controls from a lesser-privileged state'
[patent_app_type] => utility
[patent_app_number] => 13/792283
[patent_app_country] => US
[patent_app_date] => 2013-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 17242
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 294
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13792283
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/792283 | Modifying run-time-instrumentation controls from a lesser-privileged state | Mar 10, 2013 | Issued |
Array
(
[id] => 10524390
[patent_doc_number] => 09250903
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-02-02
[patent_title] => 'Determining the status of run-time-instrumentation controls'
[patent_app_type] => utility
[patent_app_number] => 13/792276
[patent_app_country] => US
[patent_app_date] => 2013-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 16444
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13792276
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/792276 | Determining the status of run-time-instrumentation controls | Mar 10, 2013 | Issued |
Array
(
[id] => 10575822
[patent_doc_number] => 09298464
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-03-29
[patent_title] => 'Instruction merging optimization'
[patent_app_type] => utility
[patent_app_number] => 13/790580
[patent_app_country] => US
[patent_app_date] => 2013-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7405
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 244
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13790580
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/790580 | Instruction merging optimization | Mar 7, 2013 | Issued |