Search

Benjamin P. Geib

Examiner (ID: 5552, Phone: (571)272-8628 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2181, 2123
Total Applications
703
Issued Applications
612
Pending Applications
6
Abandoned Applications
93

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11786553 [patent_doc_number] => 09395988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-19 [patent_title] => 'Micro-ops including packed source and destination fields' [patent_app_type] => utility [patent_app_number] => 13/790661 [patent_app_country] => US [patent_app_date] => 2013-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5495 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13790661 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/790661
Micro-ops including packed source and destination fields Mar 7, 2013 Issued
Array ( [id] => 10575822 [patent_doc_number] => 09298464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-29 [patent_title] => 'Instruction merging optimization' [patent_app_type] => utility [patent_app_number] => 13/790580 [patent_app_country] => US [patent_app_date] => 2013-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7405 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13790580 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/790580
Instruction merging optimization Mar 7, 2013 Issued
Array ( [id] => 9645036 [patent_doc_number] => 20140223149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'METHOD OF ENTROPY RANDOMIZATION ON A PARALLEL COMPUTER' [patent_app_type] => utility [patent_app_number] => 13/785515 [patent_app_country] => US [patent_app_date] => 2013-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6088 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13785515 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/785515
Method of entropy randomization on a parallel computer Mar 4, 2013 Issued
Array ( [id] => 10556148 [patent_doc_number] => 09280349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'Decode time instruction optimization for load reserve and store conditional sequences' [patent_app_type] => utility [patent_app_number] => 13/783985 [patent_app_country] => US [patent_app_date] => 2013-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10551 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13783985 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/783985
Decode time instruction optimization for load reserve and store conditional sequences Mar 3, 2013 Issued
Array ( [id] => 11226652 [patent_doc_number] => 09454374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-27 [patent_title] => 'Transforming non-contiguous instruction specifiers to contiguous instruction specifiers' [patent_app_type] => utility [patent_app_number] => 13/783321 [patent_app_country] => US [patent_app_date] => 2013-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 19397 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13783321 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/783321
Transforming non-contiguous instruction specifiers to contiguous instruction specifiers Mar 2, 2013 Issued
Array ( [id] => 11213697 [patent_doc_number] => 09442732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-13 [patent_title] => 'Running state power saving via reduced instructions per clock operation' [patent_app_type] => utility [patent_app_number] => 13/777104 [patent_app_country] => US [patent_app_date] => 2013-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4650 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13777104 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/777104
Running state power saving via reduced instructions per clock operation Feb 25, 2013 Issued
Array ( [id] => 9645035 [patent_doc_number] => 20140223148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'METHOD OF ENTROPY RANDOMIZATION ON A PARALLEL COMPUTER' [patent_app_type] => utility [patent_app_number] => 13/760510 [patent_app_country] => US [patent_app_date] => 2013-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6044 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13760510 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/760510
Method of entropy randomization on a parallel computer Feb 5, 2013 Issued
Array ( [id] => 11931552 [patent_doc_number] => 09798550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-24 [patent_title] => 'Memory access for a vector processor' [patent_app_type] => utility [patent_app_number] => 13/737290 [patent_app_country] => US [patent_app_date] => 2013-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6585 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13737290 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/737290
Memory access for a vector processor Jan 8, 2013 Issued
Array ( [id] => 13254877 [patent_doc_number] => 10140129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-27 [patent_title] => Processing core having shared front end unit [patent_app_type] => utility [patent_app_number] => 13/730719 [patent_app_country] => US [patent_app_date] => 2012-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3627 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13730719 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/730719
Processing core having shared front end unit Dec 27, 2012 Issued
Array ( [id] => 11577529 [patent_doc_number] => 09632790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'Select logic for the instruction scheduler of a multi strand out-of-order processor based on delayed reconstructed program order' [patent_app_type] => utility [patent_app_number] => 13/993794 [patent_app_country] => US [patent_app_date] => 2012-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8212 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13993794 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/993794
Select logic for the instruction scheduler of a multi strand out-of-order processor based on delayed reconstructed program order Dec 25, 2012 Issued
Array ( [id] => 8816500 [patent_doc_number] => 20130117545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-09 [patent_title] => 'High-Word Facility for Extending the Number of General Purpose Registers Available to Instructions' [patent_app_type] => utility [patent_app_number] => 13/726787 [patent_app_country] => US [patent_app_date] => 2012-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 22368 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13726787 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/726787
High-word facility for extending the number of general purpose registers available to instructions Dec 25, 2012 Issued
Array ( [id] => 13240757 [patent_doc_number] => 10133577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Vector mask driven clock gating for power efficiency of a processor [patent_app_type] => utility [patent_app_number] => 13/997791 [patent_app_country] => US [patent_app_date] => 2012-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 26 [patent_no_of_words] => 18211 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13997791 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/997791
Vector mask driven clock gating for power efficiency of a processor Dec 18, 2012 Issued
Array ( [id] => 8781954 [patent_doc_number] => 20130103929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-25 [patent_title] => 'COUPLING PROCESSORS TO EACH OTHER FOR HIGH PERFORMANCE COMPUTING (HPC)' [patent_app_type] => utility [patent_app_number] => 13/712451 [patent_app_country] => US [patent_app_date] => 2012-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9886 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13712451 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/712451
High performance computing (HPC) node having a plurality of switch coupled processors Dec 11, 2012 Issued
Array ( [id] => 12046324 [patent_doc_number] => 09823927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-21 [patent_title] => 'Range selection for data parallel programming environments' [patent_app_type] => utility [patent_app_number] => 13/690868 [patent_app_country] => US [patent_app_date] => 2012-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4227 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13690868 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/690868
Range selection for data parallel programming environments Nov 29, 2012 Issued
Array ( [id] => 9123751 [patent_doc_number] => 20130290673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'PERFORMING A DETERMINISTIC REDUCTION OPERATION IN A PARALLEL COMPUTER' [patent_app_type] => utility [patent_app_number] => 13/672740 [patent_app_country] => US [patent_app_date] => 2012-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10834 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13672740 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/672740
Performing a deterministic reduction operation in a parallel computer Nov 8, 2012 Issued
Array ( [id] => 10170945 [patent_doc_number] => 09201653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-01 [patent_title] => 'Binary translator with precise exception synchronization mechanism' [patent_app_type] => utility [patent_app_number] => 13/657651 [patent_app_country] => US [patent_app_date] => 2012-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 14843 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13657651 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/657651
Binary translator with precise exception synchronization mechanism Oct 21, 2012 Issued
Array ( [id] => 10575823 [patent_doc_number] => 09298466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-29 [patent_title] => 'Multi-threaded processor instruction balancing through instruction uncertainty' [patent_app_type] => utility [patent_app_number] => 13/651851 [patent_app_country] => US [patent_app_date] => 2012-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6690 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13651851 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/651851
Multi-threaded processor instruction balancing through instruction uncertainty Oct 14, 2012 Issued
Array ( [id] => 9398425 [patent_doc_number] => 20140095831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'APPARATUS AND METHOD FOR EFFICIENT GATHER AND SCATTER OPERATIONS' [patent_app_type] => utility [patent_app_number] => 13/631071 [patent_app_country] => US [patent_app_date] => 2012-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 15130 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13631071 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/631071
Apparatus and method for efficient gather and scatter operations Sep 27, 2012 Issued
Array ( [id] => 9745654 [patent_doc_number] => 20140281373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'DIGITAL SIGNAL PROCESSOR AND BASEBAND COMMUNICATION DEVICE' [patent_app_type] => utility [patent_app_number] => 14/350541 [patent_app_country] => US [patent_app_date] => 2012-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6353 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14350541 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/350541
DIGITAL SIGNAL PROCESSOR AND BASEBAND COMMUNICATION DEVICE Sep 16, 2012 Abandoned
Array ( [id] => 9688205 [patent_doc_number] => 20140244970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'DIGITAL SIGNAL PROCESSOR AND BASEBAND COMMUNICATION DEVICE' [patent_app_type] => utility [patent_app_number] => 14/350538 [patent_app_country] => US [patent_app_date] => 2012-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8200 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14350538 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/350538
DIGITAL SIGNAL PROCESSOR AND BASEBAND COMMUNICATION DEVICE Sep 16, 2012 Abandoned
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