Search

Benjamin P. Geib

Examiner (ID: 5552, Phone: (571)272-8628 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2181, 2123
Total Applications
703
Issued Applications
612
Pending Applications
6
Abandoned Applications
93

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9302139 [patent_doc_number] => 08650382 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-11 [patent_title] => 'Load/move and duplicate instructions for a processor' [patent_app_type] => utility [patent_app_number] => 13/620194 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4643 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13620194 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/620194
Load/move and duplicate instructions for a processor Sep 13, 2012 Issued
Array ( [id] => 8588595 [patent_doc_number] => 20130007416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'METHOD AND APPARATUS FOR SHUFFLING DATA' [patent_app_type] => utility [patent_app_number] => 13/608953 [patent_app_country] => US [patent_app_date] => 2012-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 20329 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13608953 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/608953
Method and apparatus for shuffling data Sep 9, 2012 Issued
Array ( [id] => 9308537 [patent_doc_number] => 20140047211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-13 [patent_title] => 'VECTOR REGISTER FILE' [patent_app_type] => utility [patent_app_number] => 13/572886 [patent_app_country] => US [patent_app_date] => 2012-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8448 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13572886 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/572886
Vector register file Aug 12, 2012 Issued
Array ( [id] => 9308540 [patent_doc_number] => 20140047214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-13 [patent_title] => 'VECTOR REGISTER FILE' [patent_app_type] => utility [patent_app_number] => 13/570372 [patent_app_country] => US [patent_app_date] => 2012-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8369 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13570372 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/570372
Vector register file Aug 8, 2012 Issued
Array ( [id] => 11452110 [patent_doc_number] => 09575755 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-21 [patent_title] => 'Vector processing in an active memory device' [patent_app_type] => utility [patent_app_number] => 13/566135 [patent_app_country] => US [patent_app_date] => 2012-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6927 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13566135 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/566135
Vector processing in an active memory device Aug 2, 2012 Issued
Array ( [id] => 8466879 [patent_doc_number] => 20120272047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-25 [patent_title] => 'METHOD AND APPARATUS FOR SHUFFLING DATA' [patent_app_type] => utility [patent_app_number] => 13/540576 [patent_app_country] => US [patent_app_date] => 2012-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 20303 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13540576 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/540576
Method and apparatus for shuffling data Jul 1, 2012 Issued
Array ( [id] => 11614388 [patent_doc_number] => 09652244 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-16 [patent_title] => 'Processing bypass directory tracking system and method' [patent_app_type] => utility [patent_app_number] => 13/532517 [patent_app_country] => US [patent_app_date] => 2012-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3365 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13532517 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/532517
Processing bypass directory tracking system and method Jun 24, 2012 Issued
Array ( [id] => 9264857 [patent_doc_number] => 20130346786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-26 [patent_title] => 'DYNAMIC ESCALATION OF SERVICE CONDITIONS' [patent_app_type] => utility [patent_app_number] => 13/527687 [patent_app_country] => US [patent_app_date] => 2012-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6783 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13527687 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/527687
Dynamic escalation of service conditions Jun 19, 2012 Issued
Array ( [id] => 11300443 [patent_doc_number] => 09508453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-29 [patent_title] => 'Semiconductor memory device and test method of the same' [patent_app_type] => utility [patent_app_number] => 13/494492 [patent_app_country] => US [patent_app_date] => 2012-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4607 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13494492 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/494492
Semiconductor memory device and test method of the same Jun 11, 2012 Issued
Array ( [id] => 9029605 [patent_doc_number] => 08539202 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-17 [patent_title] => 'Load/move duplicate instructions for a processor' [patent_app_type] => utility [patent_app_number] => 13/494764 [patent_app_country] => US [patent_app_date] => 2012-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4624 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13494764 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/494764
Load/move duplicate instructions for a processor Jun 11, 2012 Issued
Array ( [id] => 9326194 [patent_doc_number] => 08661231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-25 [patent_title] => 'Multi-function instruction that determines whether functions are installed on a system' [patent_app_type] => utility [patent_app_number] => 13/487929 [patent_app_country] => US [patent_app_date] => 2012-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 30 [patent_no_of_words] => 6076 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13487929 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/487929
Multi-function instruction that determines whether functions are installed on a system Jun 3, 2012 Issued
Array ( [id] => 8360831 [patent_doc_number] => 20120215988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-23 [patent_title] => 'Administering Non-Cacheable Memory Load Instructions' [patent_app_type] => utility [patent_app_number] => 13/461913 [patent_app_country] => US [patent_app_date] => 2012-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11173 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13461913 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/461913
Administering Non-Cacheable Memory Load Instructions May 1, 2012 Abandoned
Array ( [id] => 8479247 [patent_doc_number] => 20120278654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'REMOTE CABLE ACCESS POINT RESET' [patent_app_type] => utility [patent_app_number] => 13/461679 [patent_app_country] => US [patent_app_date] => 2012-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4696 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13461679 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/461679
Remote cable access point reset Apr 30, 2012 Issued
Array ( [id] => 9023436 [patent_doc_number] => 08533433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-10 [patent_title] => 'Microprocessor for executing byte compiled java code' [patent_app_type] => utility [patent_app_number] => 13/453075 [patent_app_country] => US [patent_app_date] => 2012-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 8041 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13453075 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/453075
Microprocessor for executing byte compiled java code Apr 22, 2012 Issued
Array ( [id] => 8337356 [patent_doc_number] => 20120204003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'Invoking Multi-Library Applications on a Multiple Processor System' [patent_app_type] => utility [patent_app_number] => 13/452129 [patent_app_country] => US [patent_app_date] => 2012-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4022 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13452129 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/452129
Starting other processing elements (OPEs) responsive to a determination that currently-running OPEs are inadequate to invoke a library for a multi-library application Apr 19, 2012 Issued
Array ( [id] => 9143422 [patent_doc_number] => 08583905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-12 [patent_title] => 'Runtime extraction of data parallelism' [patent_app_type] => utility [patent_app_number] => 13/435411 [patent_app_country] => US [patent_app_date] => 2012-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10945 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13435411 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/435411
Runtime extraction of data parallelism Mar 29, 2012 Issued
Array ( [id] => 11306516 [patent_doc_number] => 09513915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-06 [patent_title] => 'Instruction merging optimization' [patent_app_type] => utility [patent_app_number] => 13/432537 [patent_app_country] => US [patent_app_date] => 2012-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7100 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13432537 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/432537
Instruction merging optimization Mar 27, 2012 Issued
Array ( [id] => 9071065 [patent_doc_number] => 20130262821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'PERFORMING PREDECODE-TIME OPTIMIZED INSTRUCTIONS IN CONJUNCTION WITH PREDECODE TIME OPTIMIZED INSTRUCTION SEQUENCE CACHING' [patent_app_type] => utility [patent_app_number] => 13/432357 [patent_app_country] => US [patent_app_date] => 2012-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6255 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13432357 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/432357
Performing predecode-time optimized instructions in conjunction with predecode time optimized instruction sequence caching Mar 27, 2012 Issued
Array ( [id] => 10569123 [patent_doc_number] => 09292291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-22 [patent_title] => 'Instruction merging optimization' [patent_app_type] => utility [patent_app_number] => 13/432458 [patent_app_country] => US [patent_app_date] => 2012-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7367 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13432458 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/432458
Instruction merging optimization Mar 27, 2012 Issued
Array ( [id] => 10556147 [patent_doc_number] => 09280348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'Decode time instruction optimization for load reserve and store conditional sequences' [patent_app_type] => utility [patent_app_number] => 13/432404 [patent_app_country] => US [patent_app_date] => 2012-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10505 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13432404 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/432404
Decode time instruction optimization for load reserve and store conditional sequences Mar 27, 2012 Issued
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