Search

Benjamin P. Geib

Examiner (ID: 5552, Phone: (571)272-8628 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2181, 2123
Total Applications
703
Issued Applications
612
Pending Applications
6
Abandoned Applications
93

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9071066 [patent_doc_number] => 20130262822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'CACHING OPTIMIZED INTERNAL INSTRUCTIONS IN LOOP BUFFER' [patent_app_type] => utility [patent_app_number] => 13/432512 [patent_app_country] => US [patent_app_date] => 2012-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13432512 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/432512
Caching optimized internal instructions in loop buffer Mar 27, 2012 Issued
Array ( [id] => 9071071 [patent_doc_number] => 20130262827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'APPARATUS AND METHOD USING HYBRID LENGTH INSTRUCTION WORD' [patent_app_type] => utility [patent_app_number] => 13/431602 [patent_app_country] => US [patent_app_date] => 2012-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1631 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13431602 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/431602
APPARATUS AND METHOD USING HYBRID LENGTH INSTRUCTION WORD Mar 26, 2012 Abandoned
Array ( [id] => 12088275 [patent_doc_number] => 09842005 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-12 [patent_title] => 'Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines' [patent_app_type] => utility [patent_app_number] => 13/428438 [patent_app_country] => US [patent_app_date] => 2012-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10196 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13428438 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/428438
Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines Mar 22, 2012 Issued
Array ( [id] => 11896958 [patent_doc_number] => 09766893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-19 [patent_title] => 'Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines' [patent_app_type] => utility [patent_app_number] => 13/428440 [patent_app_country] => US [patent_app_date] => 2012-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10105 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13428440 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/428440
Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines Mar 22, 2012 Issued
Array ( [id] => 10550167 [patent_doc_number] => 09274793 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-01 [patent_title] => 'Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines' [patent_app_type] => utility [patent_app_number] => 13/428452 [patent_app_country] => US [patent_app_date] => 2012-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10188 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13428452 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/428452
Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines Mar 22, 2012 Issued
Array ( [id] => 8418951 [patent_doc_number] => 20120246452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-27 [patent_title] => 'Signature Update by Code Transformation' [patent_app_type] => utility [patent_app_number] => 13/428589 [patent_app_country] => US [patent_app_date] => 2012-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13428589 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/428589
Signature update by code transformation Mar 22, 2012 Issued
Array ( [id] => 10575818 [patent_doc_number] => 09298458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-29 [patent_title] => 'Performance of emerging applications in a virtualized environment using transient instruction streams' [patent_app_type] => utility [patent_app_number] => 13/427083 [patent_app_country] => US [patent_app_date] => 2012-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4615 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13427083 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/427083
Performance of emerging applications in a virtualized environment using transient instruction streams Mar 21, 2012 Issued
Array ( [id] => 8291725 [patent_doc_number] => 20120180052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-12 [patent_title] => 'Application Performance with Support for Re-Initiating Unconfirmed Software-Initiated Threads in Hardware' [patent_app_type] => utility [patent_app_number] => 13/427045 [patent_app_country] => US [patent_app_date] => 2012-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4363 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13427045 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/427045
Managing migration of a prefetch stream from one processor core to another processor core Mar 21, 2012 Issued
Array ( [id] => 10524389 [patent_doc_number] => 09250902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-02 [patent_title] => 'Determining the status of run-time-instrumentation controls' [patent_app_type] => utility [patent_app_number] => 13/422589 [patent_app_country] => US [patent_app_date] => 2012-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 16412 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13422589 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/422589
Determining the status of run-time-instrumentation controls Mar 15, 2012 Issued
Array ( [id] => 9044106 [patent_doc_number] => 20130246744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'MODIFYING RUN-TIME-INSTRUMENTATION CONTROLS FROM A LESSER-PRIVILEGED STATE' [patent_app_type] => utility [patent_app_number] => 13/422598 [patent_app_country] => US [patent_app_date] => 2012-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 17211 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13422598 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/422598
Modifying run-time-instrumentation controls from a lesser-privileged state Mar 15, 2012 Issued
Array ( [id] => 8280236 [patent_doc_number] => 20120174104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'Techniques for Placing Applications in Heterogeneous Virtualized Systems While Minimizing Power and Migration Cost' [patent_app_type] => utility [patent_app_number] => 13/421123 [patent_app_country] => US [patent_app_date] => 2012-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11790 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13421123 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/421123
Techniques for placing applications in heterogeneous virtualized systems while minimizing power and migration cost Mar 14, 2012 Issued
Array ( [id] => 10556146 [patent_doc_number] => 09280347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'Transforming non-contiguous instruction specifiers to contiguous instruction specifiers' [patent_app_type] => utility [patent_app_number] => 13/421657 [patent_app_country] => US [patent_app_date] => 2012-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 19343 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13421657 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/421657
Transforming non-contiguous instruction specifiers to contiguous instruction specifiers Mar 14, 2012 Issued
Array ( [id] => 8372446 [patent_doc_number] => 20120221838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-30 [patent_title] => 'SOFTWARE PROGRAMMABLE HARDWARE STATE MACHINES' [patent_app_type] => utility [patent_app_number] => 13/404350 [patent_app_country] => US [patent_app_date] => 2012-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6175 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13404350 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/404350
SOFTWARE PROGRAMMABLE HARDWARE STATE MACHINES Feb 23, 2012 Abandoned
Array ( [id] => 8639533 [patent_doc_number] => 20130031336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'EXTERNAL INTRINSIC INTERFACE' [patent_app_type] => utility [patent_app_number] => 13/398305 [patent_app_country] => US [patent_app_date] => 2012-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2724 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13398305 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/398305
External intrinsic interface Feb 15, 2012 Issued
Array ( [id] => 10150702 [patent_doc_number] => 09182991 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-10 [patent_title] => 'Multi-threaded processor instruction balancing through instruction uncertainty' [patent_app_type] => utility [patent_app_number] => 13/366999 [patent_app_country] => US [patent_app_date] => 2012-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6784 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13366999 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/366999
Multi-threaded processor instruction balancing through instruction uncertainty Feb 5, 2012 Issued
Array ( [id] => 11410846 [patent_doc_number] => 09558151 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-31 [patent_title] => 'Data processing device and data processing method thereof' [patent_app_type] => utility [patent_app_number] => 13/365928 [patent_app_country] => US [patent_app_date] => 2012-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 29 [patent_no_of_words] => 9420 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13365928 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/365928
Data processing device and data processing method thereof Feb 2, 2012 Issued
Array ( [id] => 8985093 [patent_doc_number] => 08516224 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Pipeline replay support for multicycle operations' [patent_app_type] => utility [patent_app_number] => 13/362863 [patent_app_country] => US [patent_app_date] => 2012-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 8355 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13362863 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/362863
Pipeline replay support for multicycle operations Jan 30, 2012 Issued
Array ( [id] => 9599103 [patent_doc_number] => 20140195784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'METHOD, DEVICE AND SYSTEM FOR CONTROLLING EXECUTION OF AN INSTRUCTION SEQUENCE IN A DATA STREAM ACCELERATOR' [patent_app_type] => utility [patent_app_number] => 13/993850 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 14755 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13993850 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/993850
Method, device and system for controlling execution of an instruction sequence in a data stream accelerator Dec 28, 2011 Issued
Array ( [id] => 10962718 [patent_doc_number] => 20140365748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-11 [patent_title] => 'METHOD, APPARATUS AND SYSTEM FOR DATA STREAM PROCESSING WITH A PROGRAMMABLE ACCELERATOR' [patent_app_type] => utility [patent_app_number] => 13/993826 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 14748 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13993826 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/993826
Method, apparatus and system for data stream processing with a programmable accelerator Dec 28, 2011 Issued
Array ( [id] => 11264900 [patent_doc_number] => 09489196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-08 [patent_title] => 'Multi-element instruction with different read and write masks' [patent_app_type] => utility [patent_app_number] => 13/997998 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 29 [patent_no_of_words] => 16155 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13997998 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/997998
Multi-element instruction with different read and write masks Dec 22, 2011 Issued
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